ROM_CTRL/64KB Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	15.480s	3.975ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	16.870s	270.522us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	13.410s	4.096ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	9.780s	260.149us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	9.780s	250.217us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	14.120s	19.698ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	13.410s	4.096ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.780s	250.217us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	9.260s	517.797us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	13.420s	1.024ms	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	15.500s	1.096ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	49.240s	17.623ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	29.000s	1.970ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	13.910s	4.896ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	15.390s	1.235ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	15.390s	1.235ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	16.870s	270.522us	5	5	100.00
		rom_ctrl_csr_rw	13.410s	4.096ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.780s	250.217us	5	5	100.00
		rom_ctrl_same_csr_outstanding	13.660s	984.072us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	16.870s	270.522us	5	5	100.00
		rom_ctrl_csr_rw	13.410s	4.096ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.780s	250.217us	5	5	100.00
		rom_ctrl_same_csr_outstanding	13.660s	984.072us	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	6.471m	28.301ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.053m	3.094ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.800m	2.064ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.644m	469.661us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.800m	2.064ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.471m	28.301ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.471m	28.301ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	6.471m	28.301ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.471m	28.301ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.471m	28.301ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.800m	2.064ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.800m	2.064ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	15.480s	3.975ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	15.480s	3.975ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	15.480s	3.975ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.644m	469.661us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	6.471m	28.301ms	50	50	100.00
		rom_ctrl_kmac_err_chk	29.000s	1.970ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	6.471m	28.301ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.471m	28.301ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	6.471m	28.301ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.053m	3.094ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.800m	2.064ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	5.915m	5.621ms	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			455	460	98.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.57	96.89	92.70	97.68	100.00	98.97	97.90	98.83

Failure Buckets

UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.113382320642809842232492417412046151519846498945368028152664569798445317856345
    Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 727027630 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 727027630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.rom_ctrl_stress_all_with_rand_reset.39777096482844476698175909019935109235669235385029237243173329987543406950571
    Line 297, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1131508989 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 1131508989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

ROM_CTRL/64KB Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `76588857da`