ROM_CTRL/64KB Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	15.450s	992.522us	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	16.650s	1.048ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	13.130s	1.025ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	9.600s	254.750us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	9.510s	253.980us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	10.290s	270.687us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	13.130s	1.025ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.510s	253.980us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	9.320s	260.244us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	7.870s	176.359us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	15.430s	4.098ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	50.580s	3.262ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	29.430s	8.564ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	14.250s	4.072ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	14.670s	255.369us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	14.670s	255.369us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	16.650s	1.048ms	5	5	100.00
		rom_ctrl_csr_rw	13.130s	1.025ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.510s	253.980us	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.950s	4.112ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	16.650s	1.048ms	5	5	100.00
		rom_ctrl_csr_rw	13.130s	1.025ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.510s	253.980us	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.950s	4.112ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.150m	16.829ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.414m	23.777ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.780m	1.932ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.586m	1.232ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.780m	1.932ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.150m	16.829ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.150m	16.829ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.150m	16.829ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.150m	16.829ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.150m	16.829ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.780m	1.932ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.780m	1.932ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	15.450s	992.522us	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	15.450s	992.522us	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	15.450s	992.522us	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.586m	1.232ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.150m	16.829ms	50	50	100.00
		rom_ctrl_kmac_err_chk	29.430s	8.564ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.150m	16.829ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.150m	16.829ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.150m	16.829ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.414m	23.777ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.780m	1.932ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	5.207m	13.234ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			459	460	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.49	96.89	92.13	97.68	100.00	98.62	98.05	99.06

Failure Buckets

UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 18.rom_ctrl_stress_all_with_rand_reset.30044271904740187839427316764559705204841303095931460612708976533698343443086
    Line 373, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 13528957749 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 13528957749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `76588857da`