ROM_CTRL/64KB Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: `f1535c5540`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	15.640s	9.058ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	16.450s	3.597ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	13.170s	2.048ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	9.740s	1.764ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	9.250s	1.771ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	14.790s	4.207ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	13.170s	2.048ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.250s	1.771ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	13.030s	3.923ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	9.260s	250.855us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	15.270s	1.003ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	57.720s	3.130ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	30.300s	3.866ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	13.260s	2.017ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	18.100s	984.703us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	18.100s	984.703us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	16.450s	3.597ms	5	5	100.00
		rom_ctrl_csr_rw	13.170s	2.048ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.250s	1.771ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	13.690s	503.001us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	16.450s	3.597ms	5	5	100.00
		rom_ctrl_csr_rw	13.170s	2.048ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.250s	1.771ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	13.690s	503.001us	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	6.336m	15.266ms	49	50	98.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.057m	6.115ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.840m	491.257us	5	5	100.00
		rom_ctrl_tl_intg_err	2.606m	1.009ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.840m	491.257us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.336m	15.266ms	49	50	98.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.336m	15.266ms	49	50	98.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	6.336m	15.266ms	49	50	98.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.336m	15.266ms	49	50	98.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.336m	15.266ms	49	50	98.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.840m	491.257us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.840m	491.257us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	15.640s	9.058ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	15.640s	9.058ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	15.640s	9.058ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.606m	1.009ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	6.336m	15.266ms	49	50	98.00
		rom_ctrl_kmac_err_chk	30.300s	3.866ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	6.336m	15.266ms	49	50	98.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.336m	15.266ms	49	50	98.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	6.336m	15.266ms	49	50	98.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.057m	6.115ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.840m	491.257us	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	4.552m	28.048ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			453	460	98.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.53	96.89	92.42	97.68	100.00	98.62	98.05	99.06

Failure Buckets

UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 12.rom_ctrl_stress_all_with_rand_reset.7992495392609245024833716905419653606527502165768190741065504466376390094035
    Line 333, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2395004938 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 2395004938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.rom_ctrl_stress_all_with_rand_reset.6516656551886628348733028504749913942789630251757918774125540999883106111922
    Line 260, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 237505770 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 237505770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:254) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 14.rom_ctrl_corrupt_sig_fatal_chk.27327297457276473614043208662399375784271891325423470261463137731453951855688
    Line 272, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 34956782268 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 34956782268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 43.rom_ctrl_stress_all_with_rand_reset.3357814566902810071085560539105570113492553636502269564446907383185201378782
    Line 323, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 58204224899 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 58204224899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: f1535c5540

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `f1535c5540`