ROM_CTRL/64KB Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: e45ccd274a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 11.910s 271.112us 10 10 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 20.480s 4.138ms 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 9.560s 260.160us 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 8.230s 333.007us 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 9.510s 506.813us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 13.680s 5.204ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 9.560s 260.160us 20 20 100.00
rom_ctrl_csr_aliasing 9.510s 506.813us 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 9.340s 887.421us 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 9.060s 250.511us 5 5 100.00
V1 TOTAL 75 75 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 15.730s 1.914ms 50 50 100.00
V2 stress_all rom_ctrl_stress_all 48.960s 12.556ms 50 50 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 30.030s 5.943ms 50 50 100.00
V2 alert_test rom_ctrl_alert_test 13.470s 10.883ms 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 16.650s 4.116ms 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 16.650s 4.116ms 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 20.480s 4.138ms 5 5 100.00
rom_ctrl_csr_rw 9.560s 260.160us 20 20 100.00
rom_ctrl_csr_aliasing 9.510s 506.813us 5 5 100.00
rom_ctrl_same_csr_outstanding 16.980s 999.334us 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 20.480s 4.138ms 5 5 100.00
rom_ctrl_csr_rw 9.560s 260.160us 20 20 100.00
rom_ctrl_csr_aliasing 9.510s 506.813us 5 5 100.00
rom_ctrl_same_csr_outstanding 16.980s 999.334us 20 20 100.00
V2 TOTAL 240 240 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 6.561m 22.053ms 49 50 98.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 1.387m 28.351ms 20 20 100.00
V2S tl_intg_err rom_ctrl_sec_cm 3.764m 279.468us 5 5 100.00
rom_ctrl_tl_intg_err 2.644m 725.859us 20 20 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 3.764m 279.468us 5 5 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 6.561m 22.053ms 49 50 98.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 6.561m 22.053ms 49 50 98.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 6.561m 22.053ms 49 50 98.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 6.561m 22.053ms 49 50 98.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 6.561m 22.053ms 49 50 98.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 3.764m 279.468us 5 5 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 3.764m 279.468us 5 5 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 11.910s 271.112us 10 10 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 11.910s 271.112us 10 10 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 11.910s 271.112us 10 10 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 2.644m 725.859us 20 20 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 6.561m 22.053ms 49 50 98.00
rom_ctrl_kmac_err_chk 30.030s 5.943ms 50 50 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 6.561m 22.053ms 49 50 98.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 6.561m 22.053ms 49 50 98.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 6.561m 22.053ms 49 50 98.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 1.387m 28.351ms 20 20 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 3.764m 279.468us 5 5 100.00
V2S TOTAL 94 95 98.95
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 4.756m 9.159ms 49 50 98.00
V3 TOTAL 49 50 98.00
TOTAL 458 460 99.57

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 4 4 3 75.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.42 96.89 91.99 97.68 100.00 98.28 98.05 99.06

Failure Buckets

Past Results