ROM_CTRL/64KB Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: `34b8fc33e3`

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	21.390s	5.198ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	22.660s	271.095us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.050s	983.191us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	16.830s	2.014ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	14.580s	250.180us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.330s	270.792us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.050s	983.191us	20	20	100.00
		rom_ctrl_csr_aliasing	14.580s	250.180us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	12.540s	339.796us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	19.660s	2.066ms	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	22.470s	4.504ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.016m	6.122ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	49.450s	4.099ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	21.790s	4.092ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	21.640s	251.123us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	21.640s	251.123us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	22.660s	271.095us	5	5	100.00
		rom_ctrl_csr_rw	15.050s	983.191us	20	20	100.00
		rom_ctrl_csr_aliasing	14.580s	250.180us	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.810s	729.430us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	22.660s	271.095us	5	5	100.00
		rom_ctrl_csr_rw	15.050s	983.191us	20	20	100.00
		rom_ctrl_csr_aliasing	14.580s	250.180us	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.810s	729.430us	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	9.910m	119.299ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.516m	11.611ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.577m	503.753us	5	5	100.00
		rom_ctrl_tl_intg_err	3.094m	2.295ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.577m	503.753us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.910m	119.299ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.910m	119.299ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.910m	119.299ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.910m	119.299ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.910m	119.299ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.577m	503.753us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.577m	503.753us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	21.390s	5.198ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	21.390s	5.198ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	21.390s	5.198ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	3.094m	2.295ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.910m	119.299ms	50	50	100.00
		rom_ctrl_kmac_err_chk	49.450s	4.099ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	9.910m	119.299ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.910m	119.299ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	9.910m	119.299ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.516m	11.611ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.577m	503.753us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	4.974m	8.816ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			458	460	99.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.51	96.89	92.28	97.68	100.00	98.62	98.05	99.06

Failure Buckets

UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.14963261693572201553557914679133787837802876633286609369253129312169985647667
    Line 109, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 6806395593 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 6806395593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.rom_ctrl_stress_all_with_rand_reset.21953782204525198534252684963522544020767260715368513969992144080198408459086
    Line 148, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 5488397358 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 5488397358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: 34b8fc33e3

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `34b8fc33e3`