ROM_CTRL/64KB Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: `0825c81be0`

Branch: os_regression_2024_08_22

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	14.600s	1.856ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	18.000s	1.019ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	11.960s	2.043ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	8.660s	617.352us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	8.470s	262.985us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	10.150s	2.608ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	11.960s	2.043ms	20	20	100.00
		rom_ctrl_csr_aliasing	8.470s	262.985us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	8.330s	994.196us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	11.600s	1.007ms	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	14.490s	3.954ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	47.240s	2.126ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	28.490s	24.518ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	12.810s	2.658ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	13.380s	255.721us	19	20	95.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	13.380s	255.721us	19	20	95.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	18.000s	1.019ms	5	5	100.00
		rom_ctrl_csr_rw	11.960s	2.043ms	20	20	100.00
		rom_ctrl_csr_aliasing	8.470s	262.985us	5	5	100.00
		rom_ctrl_same_csr_outstanding	12.130s	1.030ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	18.000s	1.019ms	5	5	100.00
		rom_ctrl_csr_rw	11.960s	2.043ms	20	20	100.00
		rom_ctrl_csr_aliasing	8.470s	262.985us	5	5	100.00
		rom_ctrl_same_csr_outstanding	12.130s	1.030ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	5.423m	66.392ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.294m	6.175ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.593m	873.270us	5	5	100.00
		rom_ctrl_tl_intg_err	2.346m	1.104ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.593m	873.270us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	5.423m	66.392ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	5.423m	66.392ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	5.423m	66.392ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	5.423m	66.392ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	5.423m	66.392ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.593m	873.270us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.593m	873.270us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	14.600s	1.856ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	14.600s	1.856ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	14.600s	1.856ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.346m	1.104ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	5.423m	66.392ms	50	50	100.00
		rom_ctrl_kmac_err_chk	28.490s	24.518ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	5.423m	66.392ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	5.423m	66.392ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	5.423m	66.392ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.294m	6.175ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.593m	873.270us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	4.579m	11.535ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			457	460	99.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.41	96.89	92.13	97.68	100.00	98.28	98.05	98.83

Failure Buckets

UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 40.rom_ctrl_stress_all_with_rand_reset.29919122268673859072056871384652019878206384569960029295328604812512000597049
    Line 182, in log /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2813545628 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 2813545628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.rom_ctrl_stress_all_with_rand_reset.92479546128093664457899685521877309889723734482174633467424908278385423342078
    Line 99, in log /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 7544088024 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 7544088024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:254) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_tl_errors has 1 failures.
  - 18.rom_ctrl_tl_errors.32932961907138740972471391281773305223515424859887091763529018541528140062793
    Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_tl_errors/latest/run.log
```
  UVM_ERROR @ 3296706702 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 3296706702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: 0825c81be0

Branch: os_regression_2024_08_22

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `0825c81be0`