ROM_CTRL/64KB Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: `e733a8ef8a`

Branch: os_regression_2024_08_24

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	44.123s		9	10	90.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	19.110s	171.949us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	13.510s	250.176us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	12.820s	288.814us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	22.490s	1.007ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	18.740s	8.951ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	13.510s	250.176us	20	20	100.00
		rom_ctrl_csr_aliasing	22.490s	1.007ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	13.090s	250.531us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	10.650s	181.012us	5	5	100.00
V1		TOTAL			74	75	98.67
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	24.140s	5.498ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	57.010s	833.359us	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	49.670s	39.445ms	48	50	96.00
V2	alert_test	rom_ctrl_alert_test	22.800s	19.722ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	28.750s	986.438us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	28.750s	986.438us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	19.110s	171.949us	5	5	100.00
		rom_ctrl_csr_rw	13.510s	250.176us	20	20	100.00
		rom_ctrl_csr_aliasing	22.490s	1.007ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.870s	274.497us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	19.110s	171.949us	5	5	100.00
		rom_ctrl_csr_rw	13.510s	250.176us	20	20	100.00
		rom_ctrl_csr_aliasing	22.490s	1.007ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.870s	274.497us	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	14.040m	132.597ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	2.147m	6.664ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	5.835m	382.376us	5	5	100.00
		rom_ctrl_tl_intg_err	4.025m	401.183us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	5.835m	382.376us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	14.040m	132.597ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	14.040m	132.597ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	14.040m	132.597ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	14.040m	132.597ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	14.040m	132.597ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	5.835m	382.376us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	5.835m	382.376us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	44.123s		9	10	90.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	44.123s		9	10	90.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	44.123s		9	10	90.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	4.025m	401.183us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	14.040m	132.597ms	50	50	100.00
		rom_ctrl_kmac_err_chk	49.670s	39.445ms	48	50	96.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	14.040m	132.597ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	14.040m	132.597ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	14.040m	132.597ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	2.147m	6.664ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	5.835m	382.376us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	7.987m	24.721ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			456	460	99.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.53	96.89	92.56	97.68	100.00	98.62	97.90	99.06

Failure Buckets

Job returned non-zero exit code has 2 failures:

Test rom_ctrl_smoke has 1 failures.

1.rom_ctrl_smoke.61581746418073524993002595862909806413488459864820673717666574443489784647933
Log /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_smoke/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Aug 25 04:10 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test rom_ctrl_kmac_err_chk has 1 failures.

1.rom_ctrl_kmac_err_chk.112438706265035888616846970748609191814370707879399311441982773940696488543582
Log /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_kmac_err_chk/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Aug 25 04:10 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 8.rom_ctrl_stress_all_with_rand_reset.10196577502475574728960621709324512220908362728424165071037955670869313292680
    Line 189, in log /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 13117635070 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 13117635070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:254) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_kmac_err_chk has 1 failures.
  - 32.rom_ctrl_kmac_err_chk.51473568175769997721434311608075666005036802223328137351236316541554641395403
    Line 64, in log /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 5494063681 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 5494063681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```