ROM_CTRL/64KB Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: `4674f625b3`

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	12.860s	566.286us	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	19.150s	179.747us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.970s	1.137ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	12.790s	404.546us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.510s	4.931ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.150s	544.179us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.970s	1.137ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.510s	4.931ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.110s	1.028ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	12.780s	984.607us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	22.490s	1.039ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.235m	3.547ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	37.470s	3.938ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	23.620s	1.030ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	23.460s	1.978ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	23.460s	1.978ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	19.150s	179.747us	5	5	100.00
		rom_ctrl_csr_rw	14.970s	1.137ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.510s	4.931ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.370s	1.026ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	19.150s	179.747us	5	5	100.00
		rom_ctrl_csr_rw	14.970s	1.137ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.510s	4.931ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.370s	1.026ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.180m	19.750ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.465m	8.994ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.479m	1.421ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.923m	1.224ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.479m	1.421ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.180m	19.750ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.180m	19.750ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.180m	19.750ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.180m	19.750ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.180m	19.750ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.479m	1.421ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.479m	1.421ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	12.860s	566.286us	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	12.860s	566.286us	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	12.860s	566.286us	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.923m	1.224ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.180m	19.750ms	50	50	100.00
		rom_ctrl_kmac_err_chk	37.470s	3.938ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.180m	19.750ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.180m	19.750ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.180m	19.750ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.465m	8.994ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.479m	1.421ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	4.121m	4.594ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			459	460	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.51	96.89	92.42	97.68	100.00	98.62	97.90	99.06

Failure Buckets

UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 19.rom_ctrl_stress_all_with_rand_reset.12566601140055756892136006271934513470219375625990504493578360582970441958303
    Line 129, in log /workspaces/repo/scratch/os_regression_2024_08_26/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 16927548195 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 16927548195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: 4674f625b3

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `4674f625b3`