a861deb3de| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 17.140s | 1.157ms | 10 | 10 | 100.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 26.100s | 5.048ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 19.390s | 4.111ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 15.100s | 516.099us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 12.950s | 1.074ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 16.950s | 1.076ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 19.390s | 4.111ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 12.950s | 1.074ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 15.140s | 1.960ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 15.010s | 284.132us | 5 | 5 | 100.00 |
| V1 | TOTAL | 75 | 75 | 100.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 27.130s | 4.150ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 1.246m | 6.245ms | 50 | 50 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 43.300s | 15.084ms | 50 | 50 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 23.440s | 1.026ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 21.110s | 2.020ms | 19 | 20 | 95.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 21.110s | 2.020ms | 19 | 20 | 95.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 26.100s | 5.048ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 19.390s | 4.111ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 12.950s | 1.074ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 19.240s | 172.554us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 26.100s | 5.048ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 19.390s | 4.111ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 12.950s | 1.074ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 19.240s | 172.554us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 239 | 240 | 99.58 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 8.785m | 7.629ms | 48 | 50 | 96.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 1.507m | 6.919ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 4.757m | 503.616us | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 3.187m | 1.243ms | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 4.757m | 503.616us | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.785m | 7.629ms | 48 | 50 | 96.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.785m | 7.629ms | 48 | 50 | 96.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 8.785m | 7.629ms | 48 | 50 | 96.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.785m | 7.629ms | 48 | 50 | 96.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.785m | 7.629ms | 48 | 50 | 96.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 4.757m | 503.616us | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 4.757m | 503.616us | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 17.140s | 1.157ms | 10 | 10 | 100.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 17.140s | 1.157ms | 10 | 10 | 100.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 17.140s | 1.157ms | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 3.187m | 1.243ms | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 8.785m | 7.629ms | 48 | 50 | 96.00 |
| rom_ctrl_kmac_err_chk | 43.300s | 15.084ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 8.785m | 7.629ms | 48 | 50 | 96.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.785m | 7.629ms | 48 | 50 | 96.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 8.785m | 7.629ms | 48 | 50 | 96.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 1.507m | 6.919ms | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 4.757m | 503.616us | 5 | 5 | 100.00 |
| V2S | TOTAL | 93 | 95 | 97.89 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 5.212m | 46.750ms | 47 | 50 | 94.00 |
| V3 | TOTAL | 47 | 50 | 94.00 | |||
| TOTAL | 454 | 460 | 98.70 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 5 | 83.33 |
| V2S | 4 | 4 | 3 | 75.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.42 | 96.89 | 92.13 | 97.68 | 100.00 | 98.28 | 97.90 | 99.06 |
UVM_ERROR (rom_ctrl_scoreboard.sv:254) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 3 failures:
Test rom_ctrl_tl_errors has 1 failures.
15.rom_ctrl_tl_errors.85473844477992527606500152788434442462223271727269183869071742186875430769822
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_tl_errors/latest/run.log
UVM_ERROR @ 2741341363 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 2741341363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_ctrl_corrupt_sig_fatal_chk has 2 failures.
17.rom_ctrl_corrupt_sig_fatal_chk.71575182754828038988899585929054527023239910577667196875681561586791097596202
Line 90, in log /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 28112037972 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 28112037972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.rom_ctrl_corrupt_sig_fatal_chk.77102497343865747801392459819950410300936513171745761012161106933972148516994
Line 109, in log /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 52571558797 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 52571558797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 3 failures:
18.rom_ctrl_stress_all_with_rand_reset.31554821455058941669075418043067139483242175992643423360425128401149804977446
Line 107, in log /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1438571003 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 1438571003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.rom_ctrl_stress_all_with_rand_reset.100361850604517038549536346838574788690980661760507031293824283798996654579822
Line 72, in log /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 284159364 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 284159364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.