ROM_CTRL/64KB Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: `ed1c41cd0f`

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	17.950s	1.067ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	15.590s	255.309us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	12.710s	541.300us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	13.470s	1.541ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	8.670s	514.117us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	13.920s	265.354us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	12.710s	541.300us	20	20	100.00
		rom_ctrl_csr_aliasing	8.670s	514.117us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	8.820s	383.627us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	11.790s	1.027ms	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	24.200s	1.318ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.287m	5.875ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	46.950s	7.872ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	22.400s	1.971ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	18.570s	1.830ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	18.570s	1.830ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	15.590s	255.309us	5	5	100.00
		rom_ctrl_csr_rw	12.710s	541.300us	20	20	100.00
		rom_ctrl_csr_aliasing	8.670s	514.117us	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.280s	263.091us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	15.590s	255.309us	5	5	100.00
		rom_ctrl_csr_rw	12.710s	541.300us	20	20	100.00
		rom_ctrl_csr_aliasing	8.670s	514.117us	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.280s	263.091us	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	9.921m	33.233ms	49	50	98.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.322m	6.100ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	5.063m	490.475us	5	5	100.00
		rom_ctrl_tl_intg_err	3.636m	1.195ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	5.063m	490.475us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.921m	33.233ms	49	50	98.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.921m	33.233ms	49	50	98.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.921m	33.233ms	49	50	98.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.921m	33.233ms	49	50	98.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.921m	33.233ms	49	50	98.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	5.063m	490.475us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	5.063m	490.475us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	17.950s	1.067ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	17.950s	1.067ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	17.950s	1.067ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	3.636m	1.195ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.921m	33.233ms	49	50	98.00
		rom_ctrl_kmac_err_chk	46.950s	7.872ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	9.921m	33.233ms	49	50	98.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.921m	33.233ms	49	50	98.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	9.921m	33.233ms	49	50	98.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.322m	6.100ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	5.063m	490.475us	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	4.617m	17.426ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			457	460	99.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.62	96.89	92.70	97.68	100.00	98.97	98.05	99.06

Failure Buckets

UVM_ERROR (rom_ctrl_scoreboard.sv:254) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 13.rom_ctrl_corrupt_sig_fatal_chk.18008407711180069322951926143907914875527215482985843667413618579491681955909
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 40245197223 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 40245197223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 47.rom_ctrl_stress_all_with_rand_reset.103702843673833176592462445855246518717096495923948543214663984098932536790422
    Line 193, in log /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 52732769084 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 52732769084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 9.rom_ctrl_stress_all_with_rand_reset.14310114108505076040442713042715196578646339597125590799780579669517746106178
    Line 107, in log /workspaces/repo/scratch/os_regression_2024_08_31/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1151835672 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 1151835672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: ed1c41cd0f

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `ed1c41cd0f`