RV_TIMER Simulation Results

Wednesday May 24 2023 07:09:34 UTC

GitHub Revision: `26b0ee226`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 844256362

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	46.035m	539.448ms	192	200	96.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.590s	17.866us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.720s	14.878us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.550s	468.472us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.740s	49.879us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.460s	34.832us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.720s	14.878us	20	20	100.00
		rv_timer_csr_aliasing	0.740s	49.879us	5	5	100.00
V1		TOTAL			247	255	96.86
V2	random_reset	rv_timer_random_reset	22.463m	54.601ms	49	50	98.00
V2	disabled	rv_timer_disabled	5.344m	924.108ms	47	50	94.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	22.312m	3.445s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	22.312m	3.445s	50	50	100.00
V2	stress	rv_timer_stress_all	1.309h	3.603s	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.740s	44.485us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.010s	158.516us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.010s	158.516us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.590s	17.866us	5	5	100.00
		rv_timer_csr_rw	0.720s	14.878us	20	20	100.00
		rv_timer_csr_aliasing	0.740s	49.879us	5	5	100.00
		rv_timer_same_csr_outstanding	0.880s	35.728us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.590s	17.866us	5	5	100.00
		rv_timer_csr_rw	0.720s	14.878us	20	20	100.00
		rv_timer_csr_aliasing	0.740s	49.879us	5	5	100.00
		rv_timer_same_csr_outstanding	0.880s	35.728us	20	20	100.00
V2		TOTAL			286	290	98.62
V2S	tl_intg_err	rv_timer_sec_cm	0.900s	85.027us	5	5	100.00
		rv_timer_tl_intg_err	1.410s	487.636us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.410s	487.636us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	36.741m	599.146ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			608	620	98.06

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	5	71.43
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.38	98.73	100.00	--	100.00	100.00	99.66

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 12 failures:

Test rv_timer_disabled has 3 failures.

5.rv_timer_disabled.2903714681
Line 220, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/5.rv_timer_disabled/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.rv_timer_disabled.3234719350
Line 221, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/11.rv_timer_disabled/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test rv_timer_random has 8 failures.

20.rv_timer_random.1483748205
Line 221, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/20.rv_timer_random/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

52.rv_timer_random.2186628078
Line 217, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/52.rv_timer_random/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test rv_timer_random_reset has 1 failures.

30.rv_timer_random_reset.1006136056
Line 220, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/30.rv_timer_random_reset/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---