SPI_DEVICE/1R1W Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: `8cb25a6867`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	13.500m	287.672ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.470s	52.747us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.860s	293.330us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	33.380s	545.711us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	25.220s	7.603ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.120s	1.259ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.860s	293.330us	20	20	100.00
		spi_device_csr_aliasing	25.220s	7.603ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	44.062us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.180s	1.072ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.860s	38.992us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.760s	1.628us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.720s	33.750us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	15.080s	993.499us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	15.080s	993.499us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	22.920s	7.654ms	50	50	100.00
		spi_device_tpm_sts_read	1.120s	140.295us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	58.200s	180.982ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	35.770s	51.225ms	50	50	100.00
		spi_device_flash_all	6.334m	51.498ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	31.940s	45.370ms	50	50	100.00
		spi_device_flash_all	6.334m	51.498ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	31.940s	45.370ms	50	50	100.00
		spi_device_flash_all	6.334m	51.498ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.334m	51.498ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	26.880s	5.827ms	50	50	100.00
		spi_device_flash_all	6.334m	51.498ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	26.880s	5.827ms	50	50	100.00
		spi_device_flash_all	6.334m	51.498ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	26.880s	5.827ms	50	50	100.00
		spi_device_flash_all	6.334m	51.498ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	26.880s	5.827ms	50	50	100.00
		spi_device_flash_all	6.334m	51.498ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	26.880s	5.827ms	50	50	100.00
		spi_device_flash_all	6.334m	51.498ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	35.190s	12.005ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.687m	54.122ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.687m	54.122ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.687m	54.122ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	54.860s	3.709ms	50	50	100.00
		spi_device_read_buffer_direct	23.060s	3.704ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.687m	54.122ms	50	50	100.00
		spi_device_flash_all	6.334m	51.498ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.334m	51.498ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.334m	51.498ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	28.170s	3.544ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	28.170s	3.544ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	13.500m	287.672ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.703m	749.923ms	50	50	100.00
V2	stress_all	spi_device_stress_all	14.810m	380.590ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.820s	14.025us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	17.279us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.310s	240.761us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.310s	240.761us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.470s	52.747us	5	5	100.00
		spi_device_csr_rw	2.860s	293.330us	20	20	100.00
		spi_device_csr_aliasing	25.220s	7.603ms	5	5	100.00
		spi_device_same_csr_outstanding	4.290s	651.667us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.470s	52.747us	5	5	100.00
		spi_device_csr_rw	2.860s	293.330us	20	20	100.00
		spi_device_csr_aliasing	25.220s	7.603ms	5	5	100.00
		spi_device_same_csr_outstanding	4.290s	651.667us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.250s	86.124us	5	5	100.00
		spi_device_tl_intg_err	22.810s	1.227ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.810s	1.227ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1081	1101	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.09	98.30	94.11	98.61	89.36	97.16	95.84	99.25

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.28329609386483558012969318780945158749804214064603641533230603922680462381738
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1521424 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[44])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1521424 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1521424 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[940])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.106771358734433033011141566527571172725603774331149349153156616557440707345573
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2386940 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[60])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2386940 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2386940 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[956])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.