SPI_DEVICE/1R1W Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: `01a208901a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.148m	554.216ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.450s	198.432us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.930s	230.752us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	35.280s	7.211ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	25.070s	16.392ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.050s	55.805us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.930s	230.752us	20	20	100.00
		spi_device_csr_aliasing	25.070s	16.392ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	32.916us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.440s	337.972us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.840s	16.429us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.730s	14.545us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.810s	55.622us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	6.180s	290.199us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	6.180s	290.199us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	27.500s	19.043ms	50	50	100.00
		spi_device_tpm_sts_read	1.090s	223.189us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	45.080s	15.834ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	27.600s	41.907ms	50	50	100.00
		spi_device_flash_all	6.400m	237.973ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	37.560s	24.355ms	50	50	100.00
		spi_device_flash_all	6.400m	237.973ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	37.560s	24.355ms	50	50	100.00
		spi_device_flash_all	6.400m	237.973ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.400m	237.973ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	31.980s	24.970ms	50	50	100.00
		spi_device_flash_all	6.400m	237.973ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	31.980s	24.970ms	50	50	100.00
		spi_device_flash_all	6.400m	237.973ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	31.980s	24.970ms	50	50	100.00
		spi_device_flash_all	6.400m	237.973ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	31.980s	24.970ms	50	50	100.00
		spi_device_flash_all	6.400m	237.973ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	31.980s	24.970ms	50	50	100.00
		spi_device_flash_all	6.400m	237.973ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	42.190s	12.780ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.191m	25.198ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.191m	25.198ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.191m	25.198ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.355m	12.772ms	50	50	100.00
		spi_device_read_buffer_direct	17.830s	1.488ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.191m	25.198ms	50	50	100.00
		spi_device_flash_all	6.400m	237.973ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.400m	237.973ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.400m	237.973ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	53.150s	19.351ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	53.150s	19.351ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.148m	554.216ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.869m	76.558ms	50	50	100.00
V2	stress_all	spi_device_stress_all	19.159m	632.785ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.800s	28.600us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	56.003us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.350s	824.554us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.350s	824.554us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.450s	198.432us	5	5	100.00
		spi_device_csr_rw	2.930s	230.752us	20	20	100.00
		spi_device_csr_aliasing	25.070s	16.392ms	5	5	100.00
		spi_device_same_csr_outstanding	4.420s	208.315us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.450s	198.432us	5	5	100.00
		spi_device_csr_rw	2.930s	230.752us	20	20	100.00
		spi_device_csr_aliasing	25.070s	16.392ms	5	5	100.00
		spi_device_same_csr_outstanding	4.420s	208.315us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.120s	116.526us	5	5	100.00
		spi_device_tl_intg_err	23.890s	5.503ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.890s	5.503ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1081	1101	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.08	98.31	94.11	98.61	89.36	97.16	95.84	99.20

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.34534989687098460650211494371718077861520375437624779869568540671604632714888
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    968254 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[17])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    968254 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    968254 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[913])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.14710758704662431497638039607024692223867199365450493934155569330731636609222
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1126990 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[26])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1126990 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1126990 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[922])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.