SPI_DEVICE/1R1W Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: `a182fcef27`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	14.432m	332.617ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.140s	31.248us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.770s	346.798us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	39.320s	2.707ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	25.880s	1.880ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.100s	175.100us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.770s	346.798us	20	20	100.00
		spi_device_csr_aliasing	25.880s	1.880ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	18.292us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.220s	135.647us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.940s	19.274us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.780s	1.335us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.760s	31.736us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	13.430s	747.953us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	13.430s	747.953us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	23.650s	8.650ms	50	50	100.00
		spi_device_tpm_sts_read	1.120s	137.330us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	43.640s	8.837ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	27.070s	35.237ms	50	50	100.00
		spi_device_flash_all	9.725m	179.921ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	57.190s	19.193ms	50	50	100.00
		spi_device_flash_all	9.725m	179.921ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	57.190s	19.193ms	50	50	100.00
		spi_device_flash_all	9.725m	179.921ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.725m	179.921ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	35.800s	4.502ms	50	50	100.00
		spi_device_flash_all	9.725m	179.921ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	35.800s	4.502ms	50	50	100.00
		spi_device_flash_all	9.725m	179.921ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	35.800s	4.502ms	50	50	100.00
		spi_device_flash_all	9.725m	179.921ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	35.800s	4.502ms	50	50	100.00
		spi_device_flash_all	9.725m	179.921ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	35.800s	4.502ms	50	50	100.00
		spi_device_flash_all	9.725m	179.921ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	33.040s	9.780ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.926m	38.968ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.926m	38.968ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.926m	38.968ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.001m	19.731ms	50	50	100.00
		spi_device_read_buffer_direct	20.420s	9.445ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.926m	38.968ms	50	50	100.00
		spi_device_flash_all	9.725m	179.921ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.725m	179.921ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.725m	179.921ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	25.190s	9.002ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	25.190s	9.002ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	14.432m	332.617ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.503m	662.160ms	50	50	100.00
V2	stress_all	spi_device_stress_all	16.052m	1.082s	50	50	100.00
V2	alert_test	spi_device_alert_test	0.830s	24.633us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.830s	33.904us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.570s	947.458us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.570s	947.458us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.140s	31.248us	5	5	100.00
		spi_device_csr_rw	2.770s	346.798us	20	20	100.00
		spi_device_csr_aliasing	25.880s	1.880ms	5	5	100.00
		spi_device_same_csr_outstanding	4.410s	971.480us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.140s	31.248us	5	5	100.00
		spi_device_csr_rw	2.770s	346.798us	20	20	100.00
		spi_device_csr_aliasing	25.880s	1.880ms	5	5	100.00
		spi_device_same_csr_outstanding	4.410s	971.480us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.200s	96.804us	5	5	100.00
		spi_device_tl_intg_err	23.160s	4.245ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.160s	4.245ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1081	1101	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.30	94.11	98.61	89.36	97.14	95.84	99.10

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.52158958455297657402700977817704999165201825126259870361182896136805474192006
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    931480 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[21])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    931480 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    931480 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[917])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.41381009938325761745509023189155229563578018494312884603720150118978737132410
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1147104 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[73])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1147104 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1147104 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[969])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.