SPI_DEVICE/1R1W Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: `b29ffbb03c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.246m	1.500s	49	50	98.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.500s	86.652us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.840s	361.618us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	36.130s	9.385ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.840s	608.254us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.900s	166.242us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.840s	361.618us	20	20	100.00
		spi_device_csr_aliasing	16.840s	608.254us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.720s	9.880us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.410s	136.136us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	csb_read	spi_device_csb_read	0.850s	20.238us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.740s	3.394us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.750s	43.818us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	6.950s	304.113us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	6.950s	304.113us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	20.990s	6.814ms	50	50	100.00
		spi_device_tpm_sts_read	1.050s	112.084us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	51.460s	10.952ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	37.670s	14.362ms	50	50	100.00
		spi_device_flash_all	6.788m	186.951ms	49	50	98.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	34.870s	12.863ms	50	50	100.00
		spi_device_flash_all	6.788m	186.951ms	49	50	98.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	34.870s	12.863ms	50	50	100.00
		spi_device_flash_all	6.788m	186.951ms	49	50	98.00
V2	cmd_info_slots	spi_device_flash_all	6.788m	186.951ms	49	50	98.00
V2	cmd_read_status	spi_device_intercept	23.400s	2.992ms	50	50	100.00
		spi_device_flash_all	6.788m	186.951ms	49	50	98.00
V2	cmd_read_jedec	spi_device_intercept	23.400s	2.992ms	50	50	100.00
		spi_device_flash_all	6.788m	186.951ms	49	50	98.00
V2	cmd_read_sfdp	spi_device_intercept	23.400s	2.992ms	50	50	100.00
		spi_device_flash_all	6.788m	186.951ms	49	50	98.00
V2	cmd_fast_read	spi_device_intercept	23.400s	2.992ms	50	50	100.00
		spi_device_flash_all	6.788m	186.951ms	49	50	98.00
V2	cmd_read_pipeline	spi_device_intercept	23.400s	2.992ms	50	50	100.00
		spi_device_flash_all	6.788m	186.951ms	49	50	98.00
V2	flash_cmd_upload	spi_device_upload	49.400s	66.031ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.197m	49.008ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.197m	49.008ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.197m	49.008ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	45.440s	3.830ms	50	50	100.00
		spi_device_read_buffer_direct	21.120s	7.648ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.197m	49.008ms	50	50	100.00
		spi_device_flash_all	6.788m	186.951ms	49	50	98.00
V2	quad_spi	spi_device_flash_all	6.788m	186.951ms	49	50	98.00
V2	dual_spi	spi_device_flash_all	6.788m	186.951ms	49	50	98.00
V2	4b_3b_feature	spi_device_cfg_cmd	23.010s	3.152ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	23.010s	3.152ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.246m	1.500s	49	50	98.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.249m	304.374ms	50	50	100.00
V2	stress_all	spi_device_stress_all	15.867m	97.293ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	14.858us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	160.065us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.340s	210.605us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.340s	210.605us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.500s	86.652us	5	5	100.00
		spi_device_csr_rw	2.840s	361.618us	20	20	100.00
		spi_device_csr_aliasing	16.840s	608.254us	5	5	100.00
		spi_device_same_csr_outstanding	4.350s	199.504us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.500s	86.652us	5	5	100.00
		spi_device_csr_rw	2.840s	361.618us	20	20	100.00
		spi_device_csr_aliasing	16.840s	608.254us	5	5	100.00
		spi_device_same_csr_outstanding	4.350s	199.504us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	1.170s	426.026us	5	5	100.00
		spi_device_tl_intg_err	21.110s	3.527ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.110s	3.527ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1079	1101	98.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	22	22	20	90.91
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.30	94.11	98.61	89.36	97.14	95.84	99.10

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.36756076561817432875529251402123513074935186414737083110811890709493871001580
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1163670 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[36])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1163670 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1163670 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[932])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.25128629235253811001968575784897405597849836133824855119543740856260789508996
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1506110 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[76])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1506110 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1506110 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[972])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_pass_base_vseq.sv:667) [spi_device_flash_all_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_all has 1 failures.

10.spi_device_flash_all.51722696648790616100287910200571617875230446078660379496983577366199649934927
Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 10522763180 ps: (spi_device_pass_base_vseq.sv:667) [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 10594133080 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 6/12
  UVM_INFO @ 12715771641 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 7/12
  UVM_INFO @ 15571493755 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 8/12
  UVM_INFO @ 18278736621 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 9/12

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_flash_and_tpm has 1 failures.
  - 10.spi_device_flash_and_tpm.59864658919063826010470278709319662811231218141166943114048758787446780762195
    Line 274, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```