SPI_DEVICE/1R1W Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: `32d52b8d41`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.215m	145.580ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.380s	23.855us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.820s	437.215us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	35.810s	1.841ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	25.790s	1.277ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.130s	60.908us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.820s	437.215us	20	20	100.00
		spi_device_csr_aliasing	25.790s	1.277ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.710s	40.137us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.280s	59.067us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.840s	54.560us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.740s	11.809us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	16.773us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.460s	342.335us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.460s	342.335us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	21.990s	7.197ms	50	50	100.00
		spi_device_tpm_sts_read	1.010s	253.540us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	53.480s	41.699ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	38.960s	59.528ms	50	50	100.00
		spi_device_flash_all	8.454m	70.435ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	27.430s	6.933ms	50	50	100.00
		spi_device_flash_all	8.454m	70.435ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	27.430s	6.933ms	50	50	100.00
		spi_device_flash_all	8.454m	70.435ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.454m	70.435ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	37.150s	8.757ms	50	50	100.00
		spi_device_flash_all	8.454m	70.435ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	37.150s	8.757ms	50	50	100.00
		spi_device_flash_all	8.454m	70.435ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	37.150s	8.757ms	50	50	100.00
		spi_device_flash_all	8.454m	70.435ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	37.150s	8.757ms	50	50	100.00
		spi_device_flash_all	8.454m	70.435ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	37.150s	8.757ms	50	50	100.00
		spi_device_flash_all	8.454m	70.435ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	26.260s	15.532ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.243m	49.969ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.243m	49.969ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.243m	49.969ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.125m	9.470ms	50	50	100.00
		spi_device_read_buffer_direct	23.200s	8.363ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.243m	49.969ms	50	50	100.00
		spi_device_flash_all	8.454m	70.435ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.454m	70.435ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.454m	70.435ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	23.310s	10.920ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	23.310s	10.920ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.215m	145.580ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	6.311m	158.154ms	50	50	100.00
V2	stress_all	spi_device_stress_all	11.012m	74.797ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	14.218us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	13.731us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.770s	995.688us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.770s	995.688us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.380s	23.855us	5	5	100.00
		spi_device_csr_rw	2.820s	437.215us	20	20	100.00
		spi_device_csr_aliasing	25.790s	1.277ms	5	5	100.00
		spi_device_same_csr_outstanding	4.820s	287.945us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.380s	23.855us	5	5	100.00
		spi_device_csr_rw	2.820s	437.215us	20	20	100.00
		spi_device_csr_aliasing	25.790s	1.277ms	5	5	100.00
		spi_device_same_csr_outstanding	4.820s	287.945us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.140s	553.842us	5	5	100.00
		spi_device_tl_intg_err	22.280s	3.919ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.280s	3.919ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1081	1101	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.30	94.12	98.61	89.36	97.14	95.84	99.10

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.108884549803411185438181961676945668243818188050685847541441969925285409405826
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1821753 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[65])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1821753 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1821753 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[961])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.31901328191706639870460953417501014480154800712795455196795449500684096380239
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   4764752 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[80])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   4764752 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   4764752 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[976])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.