SPI_DEVICE/1R1W Simulation Results

Saturday June 08 2024 00:41:57 UTC

GitHub Revision: `302b24f3c6`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 32491226968592963393132943636196950930602503490106290691157604759716956925599

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	14.181m	376.581ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.420s	42.899us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.850s	195.883us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	35.350s	546.730us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.840s	9.374ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.480s	243.363us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.850s	195.883us	20	20	100.00
		spi_device_csr_aliasing	24.840s	9.374ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.710s	30.533us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.340s	67.430us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.850s	20.540us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.770s	1.036us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.790s	15.652us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.860s	343.254us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.860s	343.254us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	27.600s	40.564ms	50	50	100.00
		spi_device_tpm_sts_read	1.120s	177.028us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	52.790s	9.026ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	26.140s	11.183ms	50	50	100.00
		spi_device_flash_all	10.607m	350.368ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	44.140s	55.136ms	50	50	100.00
		spi_device_flash_all	10.607m	350.368ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	44.140s	55.136ms	50	50	100.00
		spi_device_flash_all	10.607m	350.368ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	10.607m	350.368ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	31.580s	12.208ms	50	50	100.00
		spi_device_flash_all	10.607m	350.368ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	31.580s	12.208ms	50	50	100.00
		spi_device_flash_all	10.607m	350.368ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	31.580s	12.208ms	50	50	100.00
		spi_device_flash_all	10.607m	350.368ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	31.580s	12.208ms	50	50	100.00
		spi_device_flash_all	10.607m	350.368ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	31.580s	12.208ms	50	50	100.00
		spi_device_flash_all	10.607m	350.368ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	44.620s	11.167ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.786m	17.930ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.786m	17.930ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.786m	17.930ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	57.530s	4.360ms	50	50	100.00
		spi_device_read_buffer_direct	21.570s	7.300ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.786m	17.930ms	50	50	100.00
		spi_device_flash_all	10.607m	350.368ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	10.607m	350.368ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	10.607m	350.368ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	21.790s	8.651ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	21.790s	8.651ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	14.181m	376.581ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	16.231m	96.747ms	50	50	100.00
V2	stress_all	spi_device_stress_all	30.713m	199.882ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	41.760us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.830s	14.426us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.940s	751.335us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.940s	751.335us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.420s	42.899us	5	5	100.00
		spi_device_csr_rw	2.850s	195.883us	20	20	100.00
		spi_device_csr_aliasing	24.840s	9.374ms	5	5	100.00
		spi_device_same_csr_outstanding	4.330s	744.106us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.420s	42.899us	5	5	100.00
		spi_device_csr_rw	2.850s	195.883us	20	20	100.00
		spi_device_csr_aliasing	24.840s	9.374ms	5	5	100.00
		spi_device_same_csr_outstanding	4.330s	744.106us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.250s	136.103us	5	5	100.00
		spi_device_tl_intg_err	24.590s	1.030ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.590s	1.030ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1081	1101	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.09	98.30	94.11	98.61	89.36	97.16	95.84	99.25

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.103489780891025414459626425895357252157220325947482140282143277994353961376831
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1812277 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[87])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1812277 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1812277 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[983])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.2289658038349165684867808657426701640904354034550807239020058534715148427758
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   3427053 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[67])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   3427053 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   3427053 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[963])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.