SPI_DEVICE/1R1W Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: `f92a5ee77b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.614m	285.990ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.450s	50.174us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.890s	195.076us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	39.560s	5.412ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.180s	13.004ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.840s	171.007us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.890s	195.076us	20	20	100.00
		spi_device_csr_aliasing	24.180s	13.004ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.670s	20.427us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.050s	70.064us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.850s	72.989us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.760s	5.062us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.710s	16.497us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	13.330s	1.628ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	13.330s	1.628ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	21.770s	18.005ms	50	50	100.00
		spi_device_tpm_sts_read	0.950s	147.677us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	47.680s	33.708ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	31.460s	11.724ms	50	50	100.00
		spi_device_flash_all	6.030m	200.012ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	24.280s	19.383ms	50	50	100.00
		spi_device_flash_all	6.030m	200.012ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	24.280s	19.383ms	50	50	100.00
		spi_device_flash_all	6.030m	200.012ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.030m	200.012ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	30.550s	13.858ms	50	50	100.00
		spi_device_flash_all	6.030m	200.012ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	30.550s	13.858ms	50	50	100.00
		spi_device_flash_all	6.030m	200.012ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	30.550s	13.858ms	50	50	100.00
		spi_device_flash_all	6.030m	200.012ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	30.550s	13.858ms	50	50	100.00
		spi_device_flash_all	6.030m	200.012ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	30.550s	13.858ms	50	50	100.00
		spi_device_flash_all	6.030m	200.012ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	22.670s	6.616ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.802m	40.314ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.802m	40.314ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.802m	40.314ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	54.770s	12.233ms	50	50	100.00
		spi_device_read_buffer_direct	24.910s	4.115ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.802m	40.314ms	50	50	100.00
		spi_device_flash_all	6.030m	200.012ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.030m	200.012ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.030m	200.012ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	17.090s	1.253ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	17.090s	1.253ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.614m	285.990ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	7.311m	164.750ms	50	50	100.00
V2	stress_all	spi_device_stress_all	15.763m	420.134ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.800s	33.256us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.790s	14.422us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.320s	1.266ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.320s	1.266ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.450s	50.174us	5	5	100.00
		spi_device_csr_rw	2.890s	195.076us	20	20	100.00
		spi_device_csr_aliasing	24.180s	13.004ms	5	5	100.00
		spi_device_same_csr_outstanding	4.090s	2.033ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.450s	50.174us	5	5	100.00
		spi_device_csr_rw	2.890s	195.076us	20	20	100.00
		spi_device_csr_aliasing	24.180s	13.004ms	5	5	100.00
		spi_device_same_csr_outstanding	4.090s	2.033ms	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.200s	629.866us	5	5	100.00
		spi_device_tl_intg_err	22.850s	3.305ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.850s	3.305ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1081	1101	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.08	98.30	94.10	98.61	89.36	97.14	95.84	99.20

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.91067090843230378001725853755203081395789169459051440354746658167968774784025
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1689036 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[28])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1689036 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1689036 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[924])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.103094793228636304764213496461857845541448506872560124051263333951119225984996
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   3341565 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[82])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   3341565 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   3341565 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[978])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.