SPI_DEVICE/1R1W Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: `a8c9c17a8c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	7.523m	268.696ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.360s	303.530us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.960s	454.444us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	39.070s	24.611ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.220s	3.966ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.940s	54.229us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.960s	454.444us	20	20	100.00
		spi_device_csr_aliasing	24.220s	3.966ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	29.446us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.150s	131.877us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.940s	22.165us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.750s	4.704us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.760s	20.318us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	7.560s	463.370us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	7.560s	463.370us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.040s	8.000ms	50	50	100.00
		spi_device_tpm_sts_read	1.120s	93.462us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	54.000s	41.638ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	25.850s	55.600ms	50	50	100.00
		spi_device_flash_all	6.499m	441.977ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	30.530s	10.516ms	50	50	100.00
		spi_device_flash_all	6.499m	441.977ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	30.530s	10.516ms	50	50	100.00
		spi_device_flash_all	6.499m	441.977ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.499m	441.977ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	26.070s	3.037ms	50	50	100.00
		spi_device_flash_all	6.499m	441.977ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	26.070s	3.037ms	50	50	100.00
		spi_device_flash_all	6.499m	441.977ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	26.070s	3.037ms	50	50	100.00
		spi_device_flash_all	6.499m	441.977ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	26.070s	3.037ms	50	50	100.00
		spi_device_flash_all	6.499m	441.977ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	26.070s	3.037ms	50	50	100.00
		spi_device_flash_all	6.499m	441.977ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	37.960s	45.043ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.496m	65.574ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.496m	65.574ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.496m	65.574ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.535m	11.609ms	50	50	100.00
		spi_device_read_buffer_direct	17.690s	5.582ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.496m	65.574ms	50	50	100.00
		spi_device_flash_all	6.499m	441.977ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.499m	441.977ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.499m	441.977ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	17.650s	1.837ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	17.650s	1.837ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	7.523m	268.696ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.441m	293.441ms	50	50	100.00
V2	stress_all	spi_device_stress_all	12.366m	78.221ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.810s	41.884us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.860s	16.428us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.960s	2.224ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.960s	2.224ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.360s	303.530us	5	5	100.00
		spi_device_csr_rw	2.960s	454.444us	20	20	100.00
		spi_device_csr_aliasing	24.220s	3.966ms	5	5	100.00
		spi_device_same_csr_outstanding	4.760s	631.597us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.360s	303.530us	5	5	100.00
		spi_device_csr_rw	2.960s	454.444us	20	20	100.00
		spi_device_csr_aliasing	24.220s	3.966ms	5	5	100.00
		spi_device_same_csr_outstanding	4.760s	631.597us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.220s	85.493us	5	5	100.00
		spi_device_tl_intg_err	24.820s	1.129ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.820s	1.129ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1081	1101	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.98	98.30	93.94	98.62	89.36	97.14	95.45	99.05

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.3244347461547877363638566271144093655089527922457911759185504689722182390877
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1645758 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[58])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1645758 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1645758 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[954])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.63937225210421320174533606585413951099883008071121315633658563755657801154559
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   3645778 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[58])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   3645778 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   3645778 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[954])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.