SPI_DEVICE/1R1W Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: `dd5ad5fb77`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	13.122m	84.946ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.340s	38.195us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.730s	153.649us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	33.890s	2.568ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.920s	2.470ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.220s	62.342us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.730s	153.649us	20	20	100.00
		spi_device_csr_aliasing	23.920s	2.470ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	13.277us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.380s	141.722us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.840s	27.390us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.750s	4.341us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	32.750us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	13.500s	281.036us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	13.500s	281.036us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	20.060s	30.909ms	50	50	100.00
		spi_device_tpm_sts_read	1.120s	304.810us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	50.660s	9.340ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	30.860s	11.354ms	50	50	100.00
		spi_device_flash_all	5.608m	47.917ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	29.640s	10.193ms	50	50	100.00
		spi_device_flash_all	5.608m	47.917ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	29.640s	10.193ms	50	50	100.00
		spi_device_flash_all	5.608m	47.917ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.608m	47.917ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	26.490s	3.391ms	50	50	100.00
		spi_device_flash_all	5.608m	47.917ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	26.490s	3.391ms	50	50	100.00
		spi_device_flash_all	5.608m	47.917ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	26.490s	3.391ms	50	50	100.00
		spi_device_flash_all	5.608m	47.917ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	26.490s	3.391ms	50	50	100.00
		spi_device_flash_all	5.608m	47.917ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	26.490s	3.391ms	50	50	100.00
		spi_device_flash_all	5.608m	47.917ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	29.320s	9.114ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.245m	113.167ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.245m	113.167ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.245m	113.167ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	39.290s	3.927ms	50	50	100.00
		spi_device_read_buffer_direct	30.880s	4.892ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.245m	113.167ms	50	50	100.00
		spi_device_flash_all	5.608m	47.917ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.608m	47.917ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.608m	47.917ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	33.740s	13.253ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	33.740s	13.253ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	13.122m	84.946ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.774m	62.578ms	50	50	100.00
V2	stress_all	spi_device_stress_all	20.964m	277.998ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.800s	14.654us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.860s	35.100us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.470s	80.894us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.470s	80.894us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.340s	38.195us	5	5	100.00
		spi_device_csr_rw	2.730s	153.649us	20	20	100.00
		spi_device_csr_aliasing	23.920s	2.470ms	5	5	100.00
		spi_device_same_csr_outstanding	4.240s	318.098us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.340s	38.195us	5	5	100.00
		spi_device_csr_rw	2.730s	153.649us	20	20	100.00
		spi_device_csr_aliasing	23.920s	2.470ms	5	5	100.00
		spi_device_same_csr_outstanding	4.240s	318.098us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.230s	83.476us	5	5	100.00
		spi_device_tl_intg_err	23.940s	5.116ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.940s	5.116ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1081	1101	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.00	98.30	93.94	98.62	89.36	97.14	95.45	99.20

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.68190067627448564932737395479809162783035944306307221787726004918019578527515
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    876824 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[7])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    876824 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    876824 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[903])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.82878395632526051728829460044644354866901604962485603223122124695320166023536
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1183983 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[13])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1183983 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1183983 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[909])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.