SPI_DEVICE/1R1W Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: `548a3880d8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.964m	78.201ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.530s	196.564us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.040s	540.568us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	44.120s	5.478ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.280s	13.445ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.020s	129.799us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.040s	540.568us	20	20	100.00
		spi_device_csr_aliasing	15.280s	13.445ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	33.046us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.390s	268.095us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.860s	49.717us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.760s	1.105us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.810s	45.470us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.870s	906.685us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.870s	906.685us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	25.480s	38.631ms	50	50	100.00
		spi_device_tpm_sts_read	1.010s	80.884us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	56.870s	22.879ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	33.200s	46.299ms	50	50	100.00
		spi_device_flash_all	8.881m	287.992ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	24.070s	17.609ms	50	50	100.00
		spi_device_flash_all	8.881m	287.992ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	24.070s	17.609ms	50	50	100.00
		spi_device_flash_all	8.881m	287.992ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.881m	287.992ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	35.760s	7.526ms	50	50	100.00
		spi_device_flash_all	8.881m	287.992ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	35.760s	7.526ms	50	50	100.00
		spi_device_flash_all	8.881m	287.992ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	35.760s	7.526ms	50	50	100.00
		spi_device_flash_all	8.881m	287.992ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	35.760s	7.526ms	50	50	100.00
		spi_device_flash_all	8.881m	287.992ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	35.760s	7.526ms	50	50	100.00
		spi_device_flash_all	8.881m	287.992ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	41.580s	68.622ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.787m	22.762ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.787m	22.762ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.787m	22.762ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.351m	13.890ms	50	50	100.00
		spi_device_read_buffer_direct	19.350s	3.821ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.787m	22.762ms	50	50	100.00
		spi_device_flash_all	8.881m	287.992ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.881m	287.992ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.881m	287.992ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	26.900s	3.248ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	26.900s	3.248ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.964m	78.201ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.156m	68.177ms	50	50	100.00
V2	stress_all	spi_device_stress_all	10.669m	66.333ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	40.421us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.820s	12.358us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.980s	1.145ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.980s	1.145ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.530s	196.564us	5	5	100.00
		spi_device_csr_rw	3.040s	540.568us	20	20	100.00
		spi_device_csr_aliasing	15.280s	13.445ms	5	5	100.00
		spi_device_same_csr_outstanding	4.290s	714.656us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.530s	196.564us	5	5	100.00
		spi_device_csr_rw	3.040s	540.568us	20	20	100.00
		spi_device_csr_aliasing	15.280s	13.445ms	5	5	100.00
		spi_device_same_csr_outstanding	4.290s	714.656us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.410s	3.163ms	5	5	100.00
		spi_device_tl_intg_err	26.340s	8.576ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	26.340s	8.576ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1081	1101	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.99	98.30	93.93	98.62	89.36	97.14	95.45	99.15

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.95388650137791067137844854836071599297195115858123086636806840967781253803103
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   5033687 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[51])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   5033687 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   5033687 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[947])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.77652686719803264100269784245600147445755128763627536466705060532639018144378
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    914115 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[45])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    914115 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    914115 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[941])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.