SPI_DEVICE/1R1W Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: `de38ce313c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	13.831m	356.257ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.130s	20.637us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.670s	376.367us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	40.680s	19.278ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.050s	1.112ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.860s	150.731us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.670s	376.367us	20	20	100.00
		spi_device_csr_aliasing	23.050s	1.112ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	141.572us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.060s	258.483us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.900s	48.287us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.810s	1.030us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.760s	19.109us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.340s	806.122us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.340s	806.122us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	25.660s	10.099ms	50	50	100.00
		spi_device_tpm_sts_read	1.050s	99.945us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	47.080s	17.709ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	29.600s	112.858ms	50	50	100.00
		spi_device_flash_all	8.815m	291.538ms	49	50	98.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	39.670s	54.130ms	50	50	100.00
		spi_device_flash_all	8.815m	291.538ms	49	50	98.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	39.670s	54.130ms	50	50	100.00
		spi_device_flash_all	8.815m	291.538ms	49	50	98.00
V2	cmd_info_slots	spi_device_flash_all	8.815m	291.538ms	49	50	98.00
V2	cmd_read_status	spi_device_intercept	31.380s	4.518ms	50	50	100.00
		spi_device_flash_all	8.815m	291.538ms	49	50	98.00
V2	cmd_read_jedec	spi_device_intercept	31.380s	4.518ms	50	50	100.00
		spi_device_flash_all	8.815m	291.538ms	49	50	98.00
V2	cmd_read_sfdp	spi_device_intercept	31.380s	4.518ms	50	50	100.00
		spi_device_flash_all	8.815m	291.538ms	49	50	98.00
V2	cmd_fast_read	spi_device_intercept	31.380s	4.518ms	50	50	100.00
		spi_device_flash_all	8.815m	291.538ms	49	50	98.00
V2	cmd_read_pipeline	spi_device_intercept	31.380s	4.518ms	50	50	100.00
		spi_device_flash_all	8.815m	291.538ms	49	50	98.00
V2	flash_cmd_upload	spi_device_upload	45.400s	14.730ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.237m	58.798ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.237m	58.798ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.237m	58.798ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.110m	21.752ms	50	50	100.00
		spi_device_read_buffer_direct	17.350s	8.560ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.237m	58.798ms	50	50	100.00
		spi_device_flash_all	8.815m	291.538ms	49	50	98.00
V2	quad_spi	spi_device_flash_all	8.815m	291.538ms	49	50	98.00
V2	dual_spi	spi_device_flash_all	8.815m	291.538ms	49	50	98.00
V2	4b_3b_feature	spi_device_cfg_cmd	30.380s	2.566ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	30.380s	2.566ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	13.831m	356.257ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.944m	147.563ms	50	50	100.00
V2	stress_all	spi_device_stress_all	13.354m	657.320ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.780s	15.382us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	16.664us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.240s	362.281us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.240s	362.281us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.130s	20.637us	5	5	100.00
		spi_device_csr_rw	2.670s	376.367us	20	20	100.00
		spi_device_csr_aliasing	23.050s	1.112ms	5	5	100.00
		spi_device_same_csr_outstanding	4.340s	162.811us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.130s	20.637us	5	5	100.00
		spi_device_csr_rw	2.670s	376.367us	20	20	100.00
		spi_device_csr_aliasing	23.050s	1.112ms	5	5	100.00
		spi_device_same_csr_outstanding	4.340s	162.811us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	1.200s	100.700us	5	5	100.00
		spi_device_tl_intg_err	23.830s	1.341ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.830s	1.341ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1080	1101	98.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	20	90.91
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.03	98.38	93.98	98.62	89.36	97.19	95.45	99.20

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.25444589561736249094206671843112768411320308772564592800001687398006626894320
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   6928970 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[36])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   6928970 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   6928970 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[932])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.27508163881133928145183627044891649510777128400598719963927097812384825197872
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    689481 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[17])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    689481 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    689481 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[913])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

Job spi_device_1r1w-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test spi_device_flash_all has 1 failures.
  - 29.spi_device_flash_all.92945418069051258306814555099322481078656076303629995614813646784415002389629
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/29.spi_device_flash_all/latest/run.log
```
  Job ID: smart:42d52e94-7a80-4993-b5cc-bf0c0e1cbbf9
```