SPI_DEVICE/1R1W Simulation Results

Saturday June 22 2024 23:02:20 UTC

GitHub Revision: 8fdb25c8d9

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 116774179587740886356693500529232784059703555433764635649168222249757162669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.768m	750.840ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.400s	179.321us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.720s	221.637us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	25.770s	1.225ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	14.800s	209.318us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.020s	264.779us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.720s	221.637us	20	20	100.00
		spi_device_csr_aliasing	14.800s	209.318us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.720s	11.177us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.070s	60.518us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.920s	43.980us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.760s	2.909us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.750s	15.561us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	6.220s	551.057us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	6.220s	551.057us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	29.900s	10.186ms	50	50	100.00
		spi_device_tpm_sts_read	1.180s	159.141us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	44.820s	35.064ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	31.040s	11.428ms	50	50	100.00
		spi_device_flash_all	7.540m	128.789ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	37.400s	53.739ms	50	50	100.00
		spi_device_flash_all	7.540m	128.789ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	37.400s	53.739ms	50	50	100.00
		spi_device_flash_all	7.540m	128.789ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.540m	128.789ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	30.600s	14.573ms	50	50	100.00
		spi_device_flash_all	7.540m	128.789ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	30.600s	14.573ms	50	50	100.00
		spi_device_flash_all	7.540m	128.789ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	30.600s	14.573ms	50	50	100.00
		spi_device_flash_all	7.540m	128.789ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	30.600s	14.573ms	50	50	100.00
		spi_device_flash_all	7.540m	128.789ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	30.600s	14.573ms	50	50	100.00
		spi_device_flash_all	7.540m	128.789ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	39.490s	27.127ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	3.236m	17.500ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.236m	17.500ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.236m	17.500ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.178m	20.524ms	50	50	100.00
		spi_device_read_buffer_direct	13.610s	1.081ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.236m	17.500ms	50	50	100.00
		spi_device_flash_all	7.540m	128.789ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.540m	128.789ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.540m	128.789ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	27.800s	2.924ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	27.800s	2.924ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.768m	750.840ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	13.479m	582.641ms	50	50	100.00
V2	stress_all	spi_device_stress_all	24.505m	141.382ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.800s	15.793us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	44.342us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.410s	202.317us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.410s	202.317us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.400s	179.321us	5	5	100.00
		spi_device_csr_rw	2.720s	221.637us	20	20	100.00
		spi_device_csr_aliasing	14.800s	209.318us	5	5	100.00
		spi_device_same_csr_outstanding	4.530s	408.275us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.400s	179.321us	5	5	100.00
		spi_device_csr_rw	2.720s	221.637us	20	20	100.00
		spi_device_csr_aliasing	14.800s	209.318us	5	5	100.00
		spi_device_same_csr_outstanding	4.530s	408.275us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.270s	1.403ms	5	5	100.00
		spi_device_tl_intg_err	23.610s	1.043ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.610s	1.043ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1081	1101	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	93.98	98.62	89.36	97.21	95.45	99.25

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:
  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.53571776040286757897749649401375288864067413294421400209053796026181313498779
      Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4033828 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[67])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4033828 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4033828 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[963])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.86261912911395742132223222831726890344581346160052055385318586251829278223632
      Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1179419 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[4])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1179419 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1179419 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[900])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

Past Results

• Latest
• 2024.06.22_11.43.23
• 2024.06.14_07.26.15
• 2024.06.12_05.01.48
• 2024.06.11_12.03.01
• 2024.06.10_06.52.58
• 2024.06.08_13.16.24
• 2024.06.07_05.00.01