SPI_DEVICE/1R1W Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: `25e609d6bb`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.770m	128.433ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.410s	199.596us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.130s	502.683us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	34.310s	2.614ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.770s	905.964us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.290s	222.799us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.130s	502.683us	20	20	100.00
		spi_device_csr_aliasing	24.770s	905.964us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	14.017us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.050s	117.324us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.870s	36.485us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.750s	24.551us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.780s	15.737us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	16.500s	1.385ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	16.500s	1.385ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	18.430s	5.345ms	50	50	100.00
		spi_device_tpm_sts_read	1.040s	121.157us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	53.480s	10.414ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	33.820s	13.574ms	50	50	100.00
		spi_device_flash_all	9.005m	299.739ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	34.750s	18.871ms	50	50	100.00
		spi_device_flash_all	9.005m	299.739ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	34.750s	18.871ms	50	50	100.00
		spi_device_flash_all	9.005m	299.739ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.005m	299.739ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	43.870s	9.055ms	50	50	100.00
		spi_device_flash_all	9.005m	299.739ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	43.870s	9.055ms	50	50	100.00
		spi_device_flash_all	9.005m	299.739ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	43.870s	9.055ms	50	50	100.00
		spi_device_flash_all	9.005m	299.739ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	43.870s	9.055ms	50	50	100.00
		spi_device_flash_all	9.005m	299.739ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	43.870s	9.055ms	50	50	100.00
		spi_device_flash_all	9.005m	299.739ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	31.690s	47.109ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.514m	101.773ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.514m	101.773ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.514m	101.773ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.549m	10.315ms	50	50	100.00
		spi_device_read_buffer_direct	18.730s	1.655ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.514m	101.773ms	50	50	100.00
		spi_device_flash_all	9.005m	299.739ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.005m	299.739ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.005m	299.739ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	21.260s	6.455ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	21.260s	6.455ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.770m	128.433ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.042m	70.931ms	50	50	100.00
V2	stress_all	spi_device_stress_all	18.598m	137.266ms	49	50	98.00
V2	alert_test	spi_device_alert_test	0.830s	14.427us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.820s	15.414us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.000s	714.142us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.000s	714.142us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.410s	199.596us	5	5	100.00
		spi_device_csr_rw	3.130s	502.683us	20	20	100.00
		spi_device_csr_aliasing	24.770s	905.964us	5	5	100.00
		spi_device_same_csr_outstanding	4.700s	207.125us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.410s	199.596us	5	5	100.00
		spi_device_csr_rw	3.130s	502.683us	20	20	100.00
		spi_device_csr_aliasing	24.770s	905.964us	5	5	100.00
		spi_device_same_csr_outstanding	4.700s	207.125us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	1.210s	601.255us	5	5	100.00
		spi_device_tl_intg_err	20.650s	6.038ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	20.650s	6.038ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1080	1101	98.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	20	90.91
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.03	98.38	93.99	98.62	89.36	97.21	95.45	99.20

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.95668822312989940115356747617201541792457491698838761752959451114336983005438
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   3679449 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[33])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   3679449 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   3679449 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[929])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.109182813737022593400755704496203814318998307378497991831889721289726923688549
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   3846876 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[14])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   3846876 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   3846876 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[910])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_WARNING (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "busy" while containing register "spi_device_reg_block.flash_status" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

has 1 failures:

Test spi_device_stress_all has 1 failures.

31.spi_device_stress_all.98409984972821434716502441516750189171256953649877515536825690048270696443472
Line 266, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_stress_all/latest/run.log

  UVM_WARNING @ 1976187604 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "busy" while containing register "spi_device_reg_block.flash_status" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 1976187604 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "wel" while containing register "spi_device_reg_block.flash_status" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 1976187604 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "status" while containing register "spi_device_reg_block.flash_status" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 2024247282 ps: (spi_device_base_vseq.sv:126) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_csb_read_vseq] [PRE_START] - Test will run: num_trans = 36
  UVM_INFO @ 2041807282 ps: (spi_device_base_vseq.sv:126) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_csb_read_vseq] [PRE_START] - Test will run: num_trans = 35