SPI_DEVICE/1R1W Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: `6e698b4dfe`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.236m	239.736ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.460s	179.238us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.850s	472.270us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	35.260s	1.070ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	21.720s	320.739us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.980s	107.084us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.850s	472.270us	20	20	100.00
		spi_device_csr_aliasing	21.720s	320.739us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	13.509us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.490s	62.066us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.900s	21.940us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.770s	13.098us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.780s	35.443us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	7.800s	475.265us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	7.800s	475.265us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	27.670s	10.992ms	50	50	100.00
		spi_device_tpm_sts_read	1.120s	192.456us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	52.860s	45.979ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	28.080s	8.224ms	50	50	100.00
		spi_device_flash_all	7.864m	261.811ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	30.520s	50.750ms	50	50	100.00
		spi_device_flash_all	7.864m	261.811ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	30.520s	50.750ms	50	50	100.00
		spi_device_flash_all	7.864m	261.811ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.864m	261.811ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	34.880s	10.048ms	50	50	100.00
		spi_device_flash_all	7.864m	261.811ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	34.880s	10.048ms	50	50	100.00
		spi_device_flash_all	7.864m	261.811ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	34.880s	10.048ms	50	50	100.00
		spi_device_flash_all	7.864m	261.811ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	34.880s	10.048ms	50	50	100.00
		spi_device_flash_all	7.864m	261.811ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	34.880s	10.048ms	50	50	100.00
		spi_device_flash_all	7.864m	261.811ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	39.390s	12.213ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.785m	10.575ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.785m	10.575ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.785m	10.575ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.437m	10.315ms	50	50	100.00
		spi_device_read_buffer_direct	15.030s	6.154ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.785m	10.575ms	50	50	100.00
		spi_device_flash_all	7.864m	261.811ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.864m	261.811ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.864m	261.811ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	23.540s	2.949ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	23.540s	2.949ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.236m	239.736ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	15.275m	91.553ms	50	50	100.00
V2	stress_all	spi_device_stress_all	17.329m	499.800ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.770s	13.170us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.830s	30.952us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.680s	83.729us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.680s	83.729us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.460s	179.238us	5	5	100.00
		spi_device_csr_rw	2.850s	472.270us	20	20	100.00
		spi_device_csr_aliasing	21.720s	320.739us	5	5	100.00
		spi_device_same_csr_outstanding	3.980s	61.778us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.460s	179.238us	5	5	100.00
		spi_device_csr_rw	2.850s	472.270us	20	20	100.00
		spi_device_csr_aliasing	21.720s	320.739us	5	5	100.00
		spi_device_same_csr_outstanding	3.980s	61.778us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.150s	157.298us	5	5	100.00
		spi_device_tl_intg_err	25.530s	1.991ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	25.530s	1.991ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1081	1101	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	93.99	98.62	89.36	97.19	95.45	99.25

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.48642365428300283305682638215368203642983136058561375573270099355464031672635
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   3639284 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[38])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   3639284 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   3639284 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[934])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.43367667000666687989522795513718807370403900575200687338559442510999701082127
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1167551 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[93])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1167551 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1167551 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[989])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.