SPI_DEVICE/1R1W Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: `3fd3528c8c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.720m	81.200ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.470s	191.720us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.840s	194.793us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	26.260s	5.017ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.200s	3.036ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.190s	227.327us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.840s	194.793us	20	20	100.00
		spi_device_csr_aliasing	15.200s	3.036ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	11.808us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.150s	207.302us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.870s	79.325us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.830s	16.456us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.720s	15.477us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	7.910s	219.566us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	7.910s	219.566us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	22.840s	7.937ms	50	50	100.00
		spi_device_tpm_sts_read	1.070s	407.676us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	49.770s	73.462ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	31.720s	47.866ms	50	50	100.00
		spi_device_flash_all	8.109m	147.200ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	25.910s	14.878ms	50	50	100.00
		spi_device_flash_all	8.109m	147.200ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	25.910s	14.878ms	50	50	100.00
		spi_device_flash_all	8.109m	147.200ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.109m	147.200ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	26.480s	2.255ms	50	50	100.00
		spi_device_flash_all	8.109m	147.200ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	26.480s	2.255ms	50	50	100.00
		spi_device_flash_all	8.109m	147.200ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	26.480s	2.255ms	50	50	100.00
		spi_device_flash_all	8.109m	147.200ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	26.480s	2.255ms	50	50	100.00
		spi_device_flash_all	8.109m	147.200ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	26.480s	2.255ms	50	50	100.00
		spi_device_flash_all	8.109m	147.200ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	30.700s	9.173ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.885m	16.274ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.885m	16.274ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.885m	16.274ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	59.310s	4.016ms	50	50	100.00
		spi_device_read_buffer_direct	19.570s	10.811ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.885m	16.274ms	50	50	100.00
		spi_device_flash_all	8.109m	147.200ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.109m	147.200ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.109m	147.200ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	20.000s	17.612ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	20.000s	17.612ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.720m	81.200ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.898m	308.157ms	50	50	100.00
V2	stress_all	spi_device_stress_all	18.758m	475.787ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	59.584us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	20.006us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.680s	786.762us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.680s	786.762us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.470s	191.720us	5	5	100.00
		spi_device_csr_rw	2.840s	194.793us	20	20	100.00
		spi_device_csr_aliasing	15.200s	3.036ms	5	5	100.00
		spi_device_same_csr_outstanding	4.260s	759.046us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.470s	191.720us	5	5	100.00
		spi_device_csr_rw	2.840s	194.793us	20	20	100.00
		spi_device_csr_aliasing	15.200s	3.036ms	5	5	100.00
		spi_device_same_csr_outstanding	4.260s	759.046us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.230s	412.170us	5	5	100.00
		spi_device_tl_intg_err	24.700s	1.107ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.700s	1.107ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1081	1101	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.01	98.38	93.98	98.62	89.36	97.19	95.31	99.25

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.66708895655156762823735173563151942513633707531369215999411293069174660675286
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   3896173 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[70])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   3896173 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   3896173 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[966])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.22379022219021076891763658574587081019630274745927041499804681277237453312253
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2241451 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[104])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2241451 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2241451 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[1000])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.