SPI_DEVICE/1R1W Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: `625f353e9c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.231m	84.951ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.350s	73.872us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.590s	95.783us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	40.670s	5.519ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.320s	929.141us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.910s	1.030ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.590s	95.783us	20	20	100.00
		spi_device_csr_aliasing	24.320s	929.141us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	65.287us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.170s	266.397us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.900s	53.129us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.780s	6.248us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	23.228us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	9.860s	639.964us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.860s	639.964us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	17.890s	29.299ms	50	50	100.00
		spi_device_tpm_sts_read	1.050s	504.148us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	45.380s	7.478ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	26.290s	30.399ms	50	50	100.00
		spi_device_flash_all	5.803m	43.638ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	41.220s	65.016ms	50	50	100.00
		spi_device_flash_all	5.803m	43.638ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	41.220s	65.016ms	50	50	100.00
		spi_device_flash_all	5.803m	43.638ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.803m	43.638ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	37.420s	6.887ms	50	50	100.00
		spi_device_flash_all	5.803m	43.638ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	37.420s	6.887ms	50	50	100.00
		spi_device_flash_all	5.803m	43.638ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	37.420s	6.887ms	50	50	100.00
		spi_device_flash_all	5.803m	43.638ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	37.420s	6.887ms	50	50	100.00
		spi_device_flash_all	5.803m	43.638ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	37.420s	6.887ms	50	50	100.00
		spi_device_flash_all	5.803m	43.638ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	27.520s	34.810ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.867m	18.951ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.867m	18.951ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.867m	18.951ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.506m	28.389ms	50	50	100.00
		spi_device_read_buffer_direct	18.150s	7.503ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.867m	18.951ms	50	50	100.00
		spi_device_flash_all	5.803m	43.638ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.803m	43.638ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.803m	43.638ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	29.890s	3.599ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	29.890s	3.599ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.231m	84.951ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.927m	75.199ms	50	50	100.00
V2	stress_all	spi_device_stress_all	17.315m	192.026ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.780s	44.506us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.780s	55.467us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.980s	377.615us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.980s	377.615us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.350s	73.872us	5	5	100.00
		spi_device_csr_rw	2.590s	95.783us	20	20	100.00
		spi_device_csr_aliasing	24.320s	929.141us	5	5	100.00
		spi_device_same_csr_outstanding	4.420s	687.945us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.350s	73.872us	5	5	100.00
		spi_device_csr_rw	2.590s	95.783us	20	20	100.00
		spi_device_csr_aliasing	24.320s	929.141us	5	5	100.00
		spi_device_same_csr_outstanding	4.420s	687.945us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.260s	460.453us	5	5	100.00
		spi_device_tl_intg_err	22.740s	832.391us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.740s	832.391us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	11.097m	198.288ms	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	93.99	98.62	89.36	97.19	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.14568821264298868353945977537718132865905316731720236937493614785062320471773
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2065851 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[10])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2065851 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2065851 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[906])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.71771655021965031675338471081266128012394557012946541460353189934345546467820
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   4606715 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[51])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   4606715 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   4606715 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[947])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.