SPI_DEVICE/1R1W Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.955m	72.113ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.430s	75.243us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.720s	340.774us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	39.550s	5.500ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.380s	1.580ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.760s	203.389us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.720s	340.774us	20	20	100.00
		spi_device_csr_aliasing	16.380s	1.580ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.670s	11.636us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.180s	66.322us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.850s	172.358us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.730s	929.838ns	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.730s	23.169us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.750s	449.676us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.750s	449.676us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	22.500s	21.459ms	50	50	100.00
		spi_device_tpm_sts_read	1.060s	125.359us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	51.580s	37.299ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	27.810s	8.810ms	50	50	100.00
		spi_device_flash_all	9.141m	81.207ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	27.920s	8.869ms	50	50	100.00
		spi_device_flash_all	9.141m	81.207ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	27.920s	8.869ms	50	50	100.00
		spi_device_flash_all	9.141m	81.207ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.141m	81.207ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	24.550s	5.648ms	50	50	100.00
		spi_device_flash_all	9.141m	81.207ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	24.550s	5.648ms	50	50	100.00
		spi_device_flash_all	9.141m	81.207ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	24.550s	5.648ms	50	50	100.00
		spi_device_flash_all	9.141m	81.207ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	24.550s	5.648ms	50	50	100.00
		spi_device_flash_all	9.141m	81.207ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	24.550s	5.648ms	50	50	100.00
		spi_device_flash_all	9.141m	81.207ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	36.110s	11.512ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.210m	220.945ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.210m	220.945ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.210m	220.945ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	53.380s	35.907ms	50	50	100.00
		spi_device_read_buffer_direct	21.520s	1.842ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.210m	220.945ms	50	50	100.00
		spi_device_flash_all	9.141m	81.207ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.141m	81.207ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.141m	81.207ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	15.650s	1.812ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	15.650s	1.812ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.955m	72.113ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.549m	66.280ms	50	50	100.00
V2	stress_all	spi_device_stress_all	12.900m	85.320ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	52.527us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	16.860us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.120s	648.641us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.120s	648.641us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.430s	75.243us	5	5	100.00
		spi_device_csr_rw	2.720s	340.774us	20	20	100.00
		spi_device_csr_aliasing	16.380s	1.580ms	5	5	100.00
		spi_device_same_csr_outstanding	4.290s	191.431us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.430s	75.243us	5	5	100.00
		spi_device_csr_rw	2.720s	340.774us	20	20	100.00
		spi_device_csr_aliasing	16.380s	1.580ms	5	5	100.00
		spi_device_same_csr_outstanding	4.290s	191.431us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.260s	81.533us	5	5	100.00
		spi_device_tl_intg_err	22.980s	1.619ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.980s	1.619ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	9.982m	326.761ms	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	93.99	98.62	89.36	97.19	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.16158275775678600396766594950839781685865618842184407252223106791226552476680
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   3425440 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[57])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   3425440 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   3425440 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[953])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.41758892706042541412240679301161566475318978493733891267384870772149488454973
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2573590 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[9])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2573590 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2573590 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[905])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.