SPI_DEVICE/1R1W Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.067m	368.154ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.510s	48.675us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.790s	193.295us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	33.410s	616.045us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.110s	3.791ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.690s	835.557us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.790s	193.295us	20	20	100.00
		spi_device_csr_aliasing	24.110s	3.791ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.750s	21.015us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.120s	95.862us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.870s	19.863us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.770s	25.182us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	22.962us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.600s	476.592us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.600s	476.592us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	21.320s	8.177ms	50	50	100.00
		spi_device_tpm_sts_read	1.020s	140.055us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	54.030s	40.932ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	30.220s	93.459ms	50	50	100.00
		spi_device_flash_all	7.194m	385.748ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	26.160s	9.129ms	50	50	100.00
		spi_device_flash_all	7.194m	385.748ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	26.160s	9.129ms	50	50	100.00
		spi_device_flash_all	7.194m	385.748ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.194m	385.748ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	30.820s	45.203ms	50	50	100.00
		spi_device_flash_all	7.194m	385.748ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	30.820s	45.203ms	50	50	100.00
		spi_device_flash_all	7.194m	385.748ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	30.820s	45.203ms	50	50	100.00
		spi_device_flash_all	7.194m	385.748ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	30.820s	45.203ms	50	50	100.00
		spi_device_flash_all	7.194m	385.748ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	30.820s	45.203ms	50	50	100.00
		spi_device_flash_all	7.194m	385.748ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	33.780s	41.049ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.656m	11.759ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.656m	11.759ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.656m	11.759ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	56.130s	6.028ms	50	50	100.00
		spi_device_read_buffer_direct	18.190s	3.523ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.656m	11.759ms	50	50	100.00
		spi_device_flash_all	7.194m	385.748ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.194m	385.748ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.194m	385.748ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	26.700s	19.650ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	26.700s	19.650ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.067m	368.154ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.762m	115.034ms	50	50	100.00
V2	stress_all	spi_device_stress_all	16.325m	692.789ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.800s	25.546us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.840s	93.180us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.580s	251.360us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.580s	251.360us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.510s	48.675us	5	5	100.00
		spi_device_csr_rw	2.790s	193.295us	20	20	100.00
		spi_device_csr_aliasing	24.110s	3.791ms	5	5	100.00
		spi_device_same_csr_outstanding	3.990s	468.048us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.510s	48.675us	5	5	100.00
		spi_device_csr_rw	2.790s	193.295us	20	20	100.00
		spi_device_csr_aliasing	24.110s	3.791ms	5	5	100.00
		spi_device_same_csr_outstanding	3.990s	468.048us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.140s	676.729us	5	5	100.00
		spi_device_tl_intg_err	21.620s	19.578ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.620s	19.578ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	9.708m	84.947ms	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	93.99	98.62	89.36	97.19	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.13317227333496673358474912757072101854263131773571027000216882406252550008741
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2494961 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[78])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2494961 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2494961 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[974])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.38319453741016168462941471475367305957508446512345935582272944632848597278290
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2212008 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[84])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2212008 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2212008 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[980])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.