SPI_DEVICE/1R1W Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.969m	318.439ms	49	50	98.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.440s	217.682us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.680s	112.428us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	34.780s	9.767ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.630s	614.695us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.610s	153.687us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.680s	112.428us	20	20	100.00
		spi_device_csr_aliasing	15.630s	614.695us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.670s	13.238us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.310s	105.659us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	csb_read	spi_device_csb_read	0.840s	90.851us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.750s	5.659us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.720s	97.262us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	14.310s	1.597ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	14.310s	1.597ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	23.740s	20.735ms	50	50	100.00
		spi_device_tpm_sts_read	1.050s	146.365us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	54.920s	10.546ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	48.510s	17.859ms	50	50	100.00
		spi_device_flash_all	7.145m	85.335ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	31.230s	49.099ms	50	50	100.00
		spi_device_flash_all	7.145m	85.335ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	31.230s	49.099ms	50	50	100.00
		spi_device_flash_all	7.145m	85.335ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.145m	85.335ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	24.890s	8.982ms	50	50	100.00
		spi_device_flash_all	7.145m	85.335ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	24.890s	8.982ms	50	50	100.00
		spi_device_flash_all	7.145m	85.335ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	24.890s	8.982ms	50	50	100.00
		spi_device_flash_all	7.145m	85.335ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	24.890s	8.982ms	50	50	100.00
		spi_device_flash_all	7.145m	85.335ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	24.890s	8.982ms	50	50	100.00
		spi_device_flash_all	7.145m	85.335ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	51.790s	37.824ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.766m	43.260ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.766m	43.260ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.766m	43.260ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	2.542m	11.444ms	50	50	100.00
		spi_device_read_buffer_direct	17.200s	16.373ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.766m	43.260ms	50	50	100.00
		spi_device_flash_all	7.145m	85.335ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.145m	85.335ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.145m	85.335ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	26.060s	10.407ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	26.060s	10.407ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.969m	318.439ms	49	50	98.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.345m	430.930ms	50	50	100.00
V2	stress_all	spi_device_stress_all	18.063m	235.002ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	12.564us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.840s	48.027us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.240s	373.480us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.240s	373.480us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.440s	217.682us	5	5	100.00
		spi_device_csr_rw	2.680s	112.428us	20	20	100.00
		spi_device_csr_aliasing	15.630s	614.695us	5	5	100.00
		spi_device_same_csr_outstanding	4.140s	213.228us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.440s	217.682us	5	5	100.00
		spi_device_csr_rw	2.680s	112.428us	20	20	100.00
		spi_device_csr_aliasing	15.630s	614.695us	5	5	100.00
		spi_device_same_csr_outstanding	4.140s	213.228us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.160s	198.035us	5	5	100.00
		spi_device_tl_intg_err	22.120s	1.007ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.120s	1.007ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.623m	73.284ms	49	50	98.00
		TOTAL			1129	1151	98.09

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	7	87.50
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.03	98.38	93.99	98.62	89.36	97.19	95.45	99.21

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.111799272110370699660768983956786389723517487814810615059746900678545711234947
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1044231 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[22])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1044231 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1044231 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[918])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.77327335610043900782406196516470421325283786242048442499435191556608994652290
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1339570 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[75])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1339570 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1339570 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[971])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

Job spi_device_1r1w-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 12.spi_device_flash_mode_ignore_cmds.20096837167232901707976661038205301986206470759141482316051259529503990229365
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job ID: smart:7986ec0b-7e71-4c14-8935-f51935723e67
```

UVM_ERROR (spi_device_pass_base_vseq.sv:704) [flash_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_and_tpm has 1 failures.

33.spi_device_flash_and_tpm.49970248272772559708161517504726073210626646716095218382881304684199984040717
Line 285, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 3216589809 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  tl_ul_fuzzy_flash_status_q[i] = 0xb081dc
  tl_ul_fuzzy_flash_status_q[i] = 0xddba64
  UVM_INFO @ 3547040633 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 9/12
  UVM_INFO @ 3547040633 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 10/12