SPI_DEVICE/1R1W Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: `e4c5daa580`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.518m	340.555ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.170s	31.030us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.850s	216.200us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	32.460s	2.084ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.940s	3.634ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.840s	141.084us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.850s	216.200us	20	20	100.00
		spi_device_csr_aliasing	23.940s	3.634ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.710s	31.389us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.130s	57.213us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.870s	53.061us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.800s	2.717us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.750s	34.749us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	6.370s	204.663us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	6.370s	204.663us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	27.410s	37.252ms	50	50	100.00
		spi_device_tpm_sts_read	1.120s	106.186us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	40.780s	30.555ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	37.380s	15.043ms	50	50	100.00
		spi_device_flash_all	9.429m	172.581ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	27.260s	35.723ms	50	50	100.00
		spi_device_flash_all	9.429m	172.581ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	27.260s	35.723ms	50	50	100.00
		spi_device_flash_all	9.429m	172.581ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.429m	172.581ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	20.980s	9.535ms	50	50	100.00
		spi_device_flash_all	9.429m	172.581ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	20.980s	9.535ms	50	50	100.00
		spi_device_flash_all	9.429m	172.581ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	20.980s	9.535ms	50	50	100.00
		spi_device_flash_all	9.429m	172.581ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	20.980s	9.535ms	50	50	100.00
		spi_device_flash_all	9.429m	172.581ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	20.980s	9.535ms	50	50	100.00
		spi_device_flash_all	9.429m	172.581ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	34.190s	126.666ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.050m	12.114ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.050m	12.114ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.050m	12.114ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.064m	4.408ms	50	50	100.00
		spi_device_read_buffer_direct	23.380s	1.802ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.050m	12.114ms	50	50	100.00
		spi_device_flash_all	9.429m	172.581ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.429m	172.581ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.429m	172.581ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	31.150s	8.958ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	31.150s	8.958ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.518m	340.555ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.894m	289.004ms	50	50	100.00
V2	stress_all	spi_device_stress_all	15.460m	131.199ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.810s	44.436us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.820s	18.257us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.660s	375.496us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.660s	375.496us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.170s	31.030us	5	5	100.00
		spi_device_csr_rw	2.850s	216.200us	20	20	100.00
		spi_device_csr_aliasing	23.940s	3.634ms	5	5	100.00
		spi_device_same_csr_outstanding	4.200s	158.785us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.170s	31.030us	5	5	100.00
		spi_device_csr_rw	2.850s	216.200us	20	20	100.00
		spi_device_csr_aliasing	23.940s	3.634ms	5	5	100.00
		spi_device_same_csr_outstanding	4.200s	158.785us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.240s	591.338us	5	5	100.00
		spi_device_tl_intg_err	22.200s	1.671ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.200s	1.671ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.012m	75.026ms	48	50	96.00
		TOTAL			1129	1151	98.09

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.03	98.38	93.99	98.62	89.36	97.19	95.45	99.21

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.74655358093794008903445169396777362601705739349743523564808845735244030400997
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   3992801 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[7])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   3992801 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   3992801 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[903])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.29283482606520173314930618173913725813784229975786774707947258140812478342487
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2005637 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[31])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2005637 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2005637 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[927])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_pass_base_vseq.sv:704) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_mode_ignore_cmds has 1 failures.

0.spi_device_flash_mode_ignore_cmds.112745511229766225601060778131123415404143695211046670647954480733521071832627
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @ 3100797061 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 3257195778 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 0/9
  UVM_INFO @ 3257195778 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 1/9
  tl_ul_fuzzy_flash_status_q[i] = 0xb5e86e
  tl_ul_fuzzy_flash_status_q[i] = 0x2fc1f2

Job spi_device_1r1w-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 25.spi_device_flash_mode_ignore_cmds.89666308809595015437824372383630435289288321313557845913353951224835576606088
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/25.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job ID: smart:dd53bfc9-c9f2-48e6-81e8-8f179cef7a46
```