SPI_DEVICE/1R1W Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: `5fd4ecc0fc`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.782m	148.822ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.490s	52.781us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.540s	337.065us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	38.810s	1.809ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	25.400s	2.145ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.750s	204.408us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.540s	337.065us	20	20	100.00
		spi_device_csr_aliasing	25.400s	2.145ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.710s	48.855us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.020s	95.197us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.870s	60.877us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.750s	1.597us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.780s	18.267us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	7.740s	265.522us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	7.740s	265.522us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	16.460s	23.188ms	50	50	100.00
		spi_device_tpm_sts_read	1.070s	121.755us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	43.000s	15.804ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	35.890s	12.662ms	50	50	100.00
		spi_device_flash_all	8.270m	252.858ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	28.050s	9.439ms	50	50	100.00
		spi_device_flash_all	8.270m	252.858ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	28.050s	9.439ms	50	50	100.00
		spi_device_flash_all	8.270m	252.858ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.270m	252.858ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	22.250s	9.679ms	50	50	100.00
		spi_device_flash_all	8.270m	252.858ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	22.250s	9.679ms	50	50	100.00
		spi_device_flash_all	8.270m	252.858ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	22.250s	9.679ms	50	50	100.00
		spi_device_flash_all	8.270m	252.858ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	22.250s	9.679ms	50	50	100.00
		spi_device_flash_all	8.270m	252.858ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	22.250s	9.679ms	50	50	100.00
		spi_device_flash_all	8.270m	252.858ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	34.410s	48.430ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.336m	28.497ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.336m	28.497ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.336m	28.497ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	57.360s	8.311ms	50	50	100.00
		spi_device_read_buffer_direct	17.670s	1.924ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.336m	28.497ms	50	50	100.00
		spi_device_flash_all	8.270m	252.858ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.270m	252.858ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.270m	252.858ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	27.300s	10.636ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	27.300s	10.636ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.782m	148.822ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.215m	83.770ms	50	50	100.00
V2	stress_all	spi_device_stress_all	13.126m	89.113ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.820s	39.495us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	17.029us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.920s	416.698us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.920s	416.698us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.490s	52.781us	5	5	100.00
		spi_device_csr_rw	2.540s	337.065us	20	20	100.00
		spi_device_csr_aliasing	25.400s	2.145ms	5	5	100.00
		spi_device_same_csr_outstanding	4.570s	891.772us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.490s	52.781us	5	5	100.00
		spi_device_csr_rw	2.540s	337.065us	20	20	100.00
		spi_device_csr_aliasing	25.400s	2.145ms	5	5	100.00
		spi_device_same_csr_outstanding	4.570s	891.772us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.070s	63.806us	5	5	100.00
		spi_device_tl_intg_err	22.560s	3.916ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.560s	3.916ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.606m	284.261ms	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.39	93.99	98.62	89.36	97.21	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.10908359435730940756021071221484703403851921513705249592745095016457148481461
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    779989 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[53])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    779989 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    779989 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[949])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.30098318617978631907319937077458075186907593232592288618538558621954102289918
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   4098475 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[98])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   4098475 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   4098475 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[994])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.