SPI_DEVICE/1R1W Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: `372a6306e0`

Branch: os_regression_2024_09_03

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.351m	132.050ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.690s	158.638us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.750s	225.822us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	31.150s	2.082ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	28.090s	1.231ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.260s	447.798us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.750s	225.822us	20	20	100.00
		spi_device_csr_aliasing	28.090s	1.231ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.020s	31.592us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.360s	49.333us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.220s	16.564us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.100s	12.037us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.090s	15.659us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	5.870s	154.735us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.870s	154.735us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	37.120s	9.556ms	50	50	100.00
		spi_device_tpm_sts_read	1.720s	127.378us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.274m	36.589ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	54.820s	49.738ms	50	50	100.00
		spi_device_flash_all	11.431m	147.263ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	46.890s	10.469ms	50	50	100.00
		spi_device_flash_all	11.431m	147.263ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	46.890s	10.469ms	50	50	100.00
		spi_device_flash_all	11.431m	147.263ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	11.431m	147.263ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	47.300s	20.417ms	50	50	100.00
		spi_device_flash_all	11.431m	147.263ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	47.300s	20.417ms	50	50	100.00
		spi_device_flash_all	11.431m	147.263ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	47.300s	20.417ms	50	50	100.00
		spi_device_flash_all	11.431m	147.263ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	47.300s	20.417ms	50	50	100.00
		spi_device_flash_all	11.431m	147.263ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	47.300s	20.417ms	50	50	100.00
		spi_device_flash_all	11.431m	147.263ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	51.340s	65.997ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.259m	23.754ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.259m	23.754ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.259m	23.754ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.337m	15.192ms	50	50	100.00
		spi_device_read_buffer_direct	20.010s	2.160ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.259m	23.754ms	50	50	100.00
		spi_device_flash_all	11.431m	147.263ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	11.431m	147.263ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	11.431m	147.263ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	31.320s	9.103ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	31.320s	9.103ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.351m	132.050ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	13.358m	339.239ms	50	50	100.00
V2	stress_all	spi_device_stress_all	21.564m	125.852ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.160s	16.227us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.140s	26.475us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.080s	76.737us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.080s	76.737us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.690s	158.638us	5	5	100.00
		spi_device_csr_rw	3.750s	225.822us	20	20	100.00
		spi_device_csr_aliasing	28.090s	1.231ms	5	5	100.00
		spi_device_same_csr_outstanding	5.590s	220.184us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.690s	158.638us	5	5	100.00
		spi_device_csr_rw	3.750s	225.822us	20	20	100.00
		spi_device_csr_aliasing	28.090s	1.231ms	5	5	100.00
		spi_device_same_csr_outstanding	5.590s	220.184us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.900s	150.434us	5	5	100.00
		spi_device_tl_intg_err	23.560s	4.941ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.560s	4.941ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	40.239m	1.500s	49	50	98.00
		TOTAL			1130	1151	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	94.01	98.62	89.36	97.19	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.3836427000449014050193567187713312597523143380274646893829568076184546524213
Line 63, in log /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   5640238 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[16])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   5640238 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   5640238 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[912])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.112699738655637588875389257850722272278996337071881183733664091350277002531949
Line 63, in log /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2800304 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[34])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2800304 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2800304 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[930])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 12.spi_device_flash_mode_ignore_cmds.82716509702106026790739689137059086097559819194520914594393460779315823356047
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```