SPI_DEVICE/1R1W Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: `af2d1709f9`

Branch: os_regression_2024_09_08

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	17.797m	204.001ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.040s	42.331us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.790s	34.050us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	42.400s	6.271ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	21.950s	4.559ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.760s	104.633us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.790s	34.050us	20	20	100.00
		spi_device_csr_aliasing	21.950s	4.559ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.100s	11.518us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.890s	26.743us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.220s	67.878us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.110s	5.003us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	44.700s		0	1	0.00
V2	tpm_read	spi_device_tpm_rw	44.594s		49	50	98.00
V2	tpm_write	spi_device_tpm_rw	44.594s		49	50	98.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	44.681s		49	50	98.00
		spi_device_tpm_sts_read	44.621s		49	50	98.00
V2	tpm_fully_random_case	spi_device_tpm_all	58.750s	9.921ms	49	50	98.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	47.050s	114.704ms	49	50	98.00
		spi_device_flash_all	9.745m	85.739ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	44.537s		49	50	98.00
		spi_device_flash_all	9.745m	85.739ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	44.537s		49	50	98.00
		spi_device_flash_all	9.745m	85.739ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.745m	85.739ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	33.800s	3.198ms	50	50	100.00
		spi_device_flash_all	9.745m	85.739ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	33.800s	3.198ms	50	50	100.00
		spi_device_flash_all	9.745m	85.739ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	33.800s	3.198ms	50	50	100.00
		spi_device_flash_all	9.745m	85.739ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	33.800s	3.198ms	50	50	100.00
		spi_device_flash_all	9.745m	85.739ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	33.800s	3.198ms	50	50	100.00
		spi_device_flash_all	9.745m	85.739ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	38.140s	25.391ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.741m	33.648ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.741m	33.648ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.741m	33.648ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.118m	4.310ms	49	50	98.00
		spi_device_read_buffer_direct	22.310s	11.668ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.741m	33.648ms	50	50	100.00
		spi_device_flash_all	9.745m	85.739ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.745m	85.739ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.745m	85.739ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	43.670s	14.999ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	43.670s	14.999ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	17.797m	204.001ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.975m	228.605ms	50	50	100.00
V2	stress_all	spi_device_stress_all	14.860m	75.324ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.130s	150.059us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.230s	20.028us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.610s	227.838us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.610s	227.838us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.040s	42.331us	5	5	100.00
		spi_device_csr_rw	3.790s	34.050us	20	20	100.00
		spi_device_csr_aliasing	21.950s	4.559ms	5	5	100.00
		spi_device_same_csr_outstanding	5.630s	1.799ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.040s	42.331us	5	5	100.00
		spi_device_csr_rw	3.790s	34.050us	20	20	100.00
		spi_device_csr_aliasing	21.950s	4.559ms	5	5	100.00
		spi_device_same_csr_outstanding	5.630s	1.799ms	20	20	100.00
V2		TOTAL			933	961	97.09
V2S	tl_intg_err	spi_device_sec_cm	1.680s	110.351us	5	5	100.00
		spi_device_tl_intg_err	25.110s	1.107ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	25.110s	1.107ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	32.514m	1.500s	49	50	98.00
		TOTAL			1122	1151	97.48

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	13	59.09
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.36	98.36	93.99	93.90	89.36	97.19	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.40790640669930792938044197664748577233811844407164537794747797178787863747485
Line 63, in log /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    770025 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[90])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    770025 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    770025 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[986])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.74270277492032254375237211210350889033127058896858298458546228499994027880912
Line 63, in log /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   4216740 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[11])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   4216740 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   4216740 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[907])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

Job returned non-zero exit code has 7 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.106378481450812245865257333483839247057569273833863958133597148957853387295096
Log /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep  9 11:28 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test spi_device_tpm_read_hw_reg has 1 failures.

0.spi_device_tpm_read_hw_reg.1007128355049700287679293221956565701903725432519349042961827849017816273579
Log /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_tpm_read_hw_reg/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep  9 11:28 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test spi_device_tpm_all has 1 failures.

0.spi_device_tpm_all.74923299586500265205884587065211905371245007257537281336402586521196866080248
Log /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_tpm_all/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep  9 11:28 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test spi_device_tpm_sts_read has 1 failures.

0.spi_device_tpm_sts_read.84609693572640717680172256866844312360833467325443742931750777003679823892152
Log /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_tpm_sts_read/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep  9 11:28 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test spi_device_tpm_rw has 1 failures.

0.spi_device_tpm_rw.4461347885526752052012698863987442432933275087280723720856834981269855722224
Log /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_tpm_rw/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep  9 11:28 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

... and 2 more tests.

UVM_ERROR (spi_device_scoreboard.sv:2338) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufWatermark mismatch, act (*) != exp * has 1 failures:

Test spi_device_flash_mode has 1 failures.

9.spi_device_flash_mode.37421944583740909556877519432687898138678203785720375218090024636795340448314
Line 63, in log /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode/latest/run.log

  UVM_ERROR @ 157509695 ps: (spi_device_scoreboard.sv:2338) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
  UVM_ERROR @ 889656915 ps: (spi_device_scoreboard.sv:2803) [uvm_test_top.env.scoreboard] Check failed |(intr_trigger_pending & interrupt_mask) == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 889656915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 26.spi_device_flash_mode_ignore_cmds.45250399483861779836324071084389596478350525614179818200842447808659636310113
    Line 91, in log /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```