2723ca659d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_flash_and_tpm | 24.500s | 2.114ms | 0 | 50 | 0.00 |
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.470s | 97.906us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_device_csr_rw | 3.010s | 122.463us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 37.420s | 3.613ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_device_csr_aliasing | 20.980s | 5.966ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 3.840s | 132.668us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 3.010s | 122.463us | 20 | 20 | 100.00 |
| spi_device_csr_aliasing | 20.980s | 5.966ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_device_mem_walk | 0.710s | 39.677us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_device_mem_partial_access | 2.000s | 91.312us | 5 | 5 | 100.00 |
| V1 | TOTAL | 65 | 115 | 56.52 | |||
| V2 | csb_read | spi_device_csb_read | 0.830s | 22.519us | 50 | 50 | 100.00 |
| V2 | mem_parity | spi_device_mem_parity | 1.150s | 32.466us | 20 | 20 | 100.00 |
| V2 | mem_cfg | spi_device_ram_cfg | 0.770s | 42.290us | 20 | 20 | 100.00 |
| V2 | tpm_read | spi_device_tpm_rw | 7.770s | 196.457us | 50 | 50 | 100.00 |
| V2 | tpm_write | spi_device_tpm_rw | 7.770s | 196.457us | 50 | 50 | 100.00 |
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 33.100s | 251.212ms | 50 | 50 | 100.00 |
| spi_device_tpm_sts_read | 1.220s | 145.403us | 50 | 50 | 100.00 | ||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 59.040s | 11.978ms | 50 | 50 | 100.00 |
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 39.760s | 13.641ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 10.460s | 5.215ms | 1 | 50 | 2.00 | ||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 46.480s | 239.470ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 10.460s | 5.215ms | 1 | 50 | 2.00 | ||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 46.480s | 239.470ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 10.460s | 5.215ms | 1 | 50 | 2.00 | ||
| V2 | cmd_info_slots | spi_device_flash_all | 10.460s | 5.215ms | 1 | 50 | 2.00 |
| V2 | cmd_read_status | spi_device_intercept | 37.540s | 32.947ms | 42 | 50 | 84.00 |
| spi_device_flash_all | 10.460s | 5.215ms | 1 | 50 | 2.00 | ||
| V2 | cmd_read_jedec | spi_device_intercept | 37.540s | 32.947ms | 42 | 50 | 84.00 |
| spi_device_flash_all | 10.460s | 5.215ms | 1 | 50 | 2.00 | ||
| V2 | cmd_read_sfdp | spi_device_intercept | 37.540s | 32.947ms | 42 | 50 | 84.00 |
| spi_device_flash_all | 10.460s | 5.215ms | 1 | 50 | 2.00 | ||
| V2 | cmd_fast_read | spi_device_intercept | 37.540s | 32.947ms | 42 | 50 | 84.00 |
| spi_device_flash_all | 10.460s | 5.215ms | 1 | 50 | 2.00 | ||
| V2 | cmd_read_pipeline | spi_device_intercept | 37.540s | 32.947ms | 42 | 50 | 84.00 |
| spi_device_flash_all | 10.460s | 5.215ms | 1 | 50 | 2.00 | ||
| V2 | flash_cmd_upload | spi_device_upload | 43.940s | 255.703ms | 34 | 50 | 68.00 |
| V2 | mailbox_command | spi_device_mailbox | 2.664m | 41.303ms | 45 | 50 | 90.00 |
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 2.664m | 41.303ms | 45 | 50 | 90.00 |
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 2.664m | 41.303ms | 45 | 50 | 90.00 |
| V2 | cmd_read_buffer | spi_device_flash_mode | 3.037m | 50.789ms | 44 | 50 | 88.00 |
| spi_device_read_buffer_direct | 23.870s | 6.089ms | 50 | 50 | 100.00 | ||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 2.664m | 41.303ms | 45 | 50 | 90.00 |
| spi_device_flash_all | 10.460s | 5.215ms | 1 | 50 | 2.00 | ||
| V2 | quad_spi | spi_device_flash_all | 10.460s | 5.215ms | 1 | 50 | 2.00 |
| V2 | dual_spi | spi_device_flash_all | 10.460s | 5.215ms | 1 | 50 | 2.00 |
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 39.250s | 12.201ms | 28 | 50 | 56.00 |
| V2 | write_enable_disable | spi_device_cfg_cmd | 39.250s | 12.201ms | 28 | 50 | 56.00 |
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 24.500s | 2.114ms | 0 | 50 | 0.00 |
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 38.560s | 4.010ms | 0 | 50 | 0.00 |
| V2 | stress_all | spi_device_stress_all | 15.230s | 10.087ms | 8 | 50 | 16.00 |
| V2 | alert_test | spi_device_alert_test | 0.810s | 24.216us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_device_intr_test | 0.790s | 14.545us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 5.190s | 506.673us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_device_tl_errors | 5.190s | 506.673us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.470s | 97.906us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 3.010s | 122.463us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 20.980s | 5.966ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.400s | 1.340ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.470s | 97.906us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 3.010s | 122.463us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 20.980s | 5.966ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.400s | 1.340ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 782 | 980 | 79.80 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 1.230s | 86.578us | 5 | 5 | 100.00 |
| spi_device_tl_intg_err | 23.760s | 1.113ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 23.760s | 1.113ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 872 | 1120 | 77.86 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 22 | 22 | 14 | 63.64 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 92.12 | 97.57 | 92.92 | 98.61 | 80.85 | 95.97 | 90.92 | 88.03 |
Job spi_device_2p-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 211 failures:
0.spi_device_cfg_cmd.63063637766174176882167151544669948406333270187731750373201682270745920802221
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_cfg_cmd/latest/run.log
Job ID: smart:64a195ac-a872-4596-8874-0cec30443cb7
2.spi_device_cfg_cmd.109556349694115453691032995345979699931530958727492304144047054445339133503518
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_cfg_cmd/latest/run.log
Job ID: smart:5a6f37d5-8dc0-4ece-ab43-b4032caeb1a9
... and 19 more failures.
0.spi_device_flash_mode.111118807061898085861055062146175997601763914865373695651519446890402677745815
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_mode/latest/run.log
Job ID: smart:bb741dfe-0c58-4bb6-a441-e657cb794810
21.spi_device_flash_mode.100201366564904156351857655131440043216080949196029317825728410423953896074709
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/21.spi_device_flash_mode/latest/run.log
Job ID: smart:71c0fb52-0e47-4925-8666-9eb50f81c2a8
... and 4 more failures.
0.spi_device_flash_all.15699429131524198834097050782761542724420395764741120522567965791688670766577
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_all/latest/run.log
Job ID: smart:9e16160e-53f2-4e97-afb5-89df42005099
1.spi_device_flash_all.91768071518805592069069769635716495177807416035786682688545979948960765242678
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_all/latest/run.log
Job ID: smart:bf1bd776-091f-4e90-9723-67ac7c9e587a
... and 44 more failures.
0.spi_device_flash_and_tpm.68011442604072328684261384292217951250543910037302346969254218023806346339286
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:baec04f9-ffed-4349-b52f-bb104629f72c
1.spi_device_flash_and_tpm.23758900603993708175426034149142921306263124952934386224185715693970345441301
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:4d5ae665-833a-48fd-8e48-65c1b6473c95
... and 43 more failures.
0.spi_device_flash_and_tpm_min_idle.32839704156475596047456548691717840669296930427833898774932292626232215046452
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:a14698eb-d3ee-4885-b6a0-056af024d15d
1.spi_device_flash_and_tpm_min_idle.66376603552816684737924617962239765669792624540207230176564239646938425652051
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:c14dd543-9ea0-40ee-8fa4-e512c1eb3a3f
... and 39 more failures.
UVM_FATAL (spi_device_scoreboard.sv:726) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 19 failures:
Test spi_device_upload has 7 failures.
1.spi_device_upload.78081656982387190916588971255340228329783482421824514747210135126843857813345
Line 259, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_upload/latest/run.log
UVM_FATAL @ 98175810497 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 98175810497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.spi_device_upload.70001038548688061464687680302731344959042161344265139842797345534193473484699
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_upload/latest/run.log
UVM_FATAL @ 235568874 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 235568874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Test spi_device_flash_all has 2 failures.
2.spi_device_flash_all.106419877473562552066710032483493152744900581601451975982361725882234889408061
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_flash_all/latest/run.log
UVM_FATAL @ 5214714784 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 5214714784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.spi_device_flash_all.63637230063127057381876259701561672821830248047332749615262314349042963327003
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/33.spi_device_flash_all/latest/run.log
UVM_FATAL @ 4392210116 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 4392210116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_flash_and_tpm has 3 failures.
3.spi_device_flash_and_tpm.42906608958275357712954455076660083479959862818294935724434392245585049352232
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 1001431452 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1001431452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.spi_device_flash_and_tpm.45795803537527818971354189335843999679195501770476074579963721298980021729192
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 2114175765 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2114175765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_device_flash_and_tpm_min_idle has 5 failures.
3.spi_device_flash_and_tpm_min_idle.39658783404409744878704698921778723313380961086109199442936268934519601876748
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 2384748863 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2384748863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.spi_device_flash_and_tpm_min_idle.60539485202677991248778845446644342442634623361516480384310531905777527211155
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 757191380 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 757191380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test spi_device_stress_all has 2 failures.
20.spi_device_stress_all.54938294203675500937855771769995919228724844059152586167456822417725220916835
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/20.spi_device_stress_all/latest/run.log
UVM_FATAL @ 651883372 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 651883372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.spi_device_stress_all.90373168326419524416468777190697565956322776543868412416522427305929150578337
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_stress_all/latest/run.log
UVM_FATAL @ 937355945 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 937355945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 16 failures:
Test spi_device_upload has 9 failures.
3.spi_device_upload.37081869685689039188867170621494864309507988949785287515723837674585609206954
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_upload/latest/run.log
UVM_ERROR @ 402583401 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 464799585 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 466502245 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 3, test op = 0x5
UVM_INFO @ 628071341 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 4, test op = 0x76
UVM_INFO @ 760039789 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 5, test op = 0x76
18.spi_device_upload.58789339782935347856511471671030097552853006631298841676749423962355188590240
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_upload/latest/run.log
UVM_ERROR @ 221178606 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 324698606 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 325422606 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 2, test op = 0x32
UVM_INFO @ 1101482606 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 3, test op = 0x54
UVM_ERROR @ 1188218606 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
... and 7 more failures.
Test spi_device_flash_and_tpm has 2 failures.
6.spi_device_flash_and_tpm.7630779810609827077948775284162279924553827522689009428756789559635035062721
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 505223769 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 1418778359 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 3713285875 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 3713285875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.spi_device_flash_and_tpm.23654585815557044238086148781835757366102184305669836735138094787363977562075
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 90955345 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x876f29) != exp '{'{other_status:'h21dbca, wel:'h0, busy:'h0}, '{other_status:'h21dbca, wel:'h0, busy:'h0}}
UVM_FATAL @ 94912211 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 94912211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_flash_all has 1 failures.
17.spi_device_flash_all.36019868350202216274477828754660341063947402819095875604121271783512123456363
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_flash_all/latest/run.log
UVM_ERROR @ 68761888 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 1175760837 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1175760837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_flash_and_tpm_min_idle has 3 failures.
21.spi_device_flash_and_tpm_min_idle.23933550921199965803686697236892060505480418665507907115761151855705000414366
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 5090343151 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 5179298152 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 5179298152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.spi_device_flash_and_tpm_min_idle.33397294003127936681418540217724993249398657777311896523670625754411565526786
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 271384479 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 1460115269 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 2/10
UVM_INFO @ 1631914754 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 3/10
UVM_INFO @ 1886980032 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 4/10
UVM_INFO @ 2364059934 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 5/10
... and 1 more failures.
Test spi_device_stress_all has 1 failures.
23.spi_device_stress_all.21317296430161120897705550334300298224961234036904356880316571183975736037947
Line 260, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_stress_all/latest/run.log
UVM_ERROR @ 9983153114 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 10087119198 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 10087119198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:
45.spi_device_flash_and_tpm_min_idle.67008444345847592250636783190498762162820953993091439428334104624091180193884
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 92229676 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xbede32) != exp '{'{other_status:'h2fb78c, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h2fb78c, wel:'h0, busy:'h0}, '{other_status:'h2fb78c, wel:'h0, busy:'h0}}
UVM_ERROR @ 103877780 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h2fb78c, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 104044436 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h2fb78c, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 104211092 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h2fb78c, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 104377748 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h2fb78c, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:
49.spi_device_cfg_cmd.105478438996648798328611411766108477332313094813757904407960150663702644861857
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 60450296 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x96e77e) != exp '{'{other_status:'h25b9df, wel:'h0, busy:'h0}, '{other_status:'h25b9df, wel:'h0, busy:'h0}, '{other_status:'h33fbe, wel:'h0, busy:'h0}}
UVM_ERROR @ 60544049 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x96e77e) != exp '{'{other_status:'h25b9df, wel:'h0, busy:'h0}, '{other_status:'h25b9df, wel:'h0, busy:'h0}, '{other_status:'h33fbe, wel:'h0, busy:'h0}}
UVM_ERROR @ 61127401 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x96e77e) != exp '{'{other_status:'h25b9df, wel:'h0, busy:'h0}, '{other_status:'h25b9df, wel:'h0, busy:'h0}, '{other_status:'h33fbe, wel:'h0, busy:'h0}}
UVM_ERROR @ 61241988 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x96e77e) != exp '{'{other_status:'h25b9df, wel:'h0, busy:'h0}, '{other_status:'h25b9df, wel:'h0, busy:'h0}, '{other_status:'h33fbe, wel:'h0, busy:'h0}}
UVM_ERROR @ 61408660 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x96e77e) != exp '{'{other_status:'h25b9df, wel:'h0, busy:'h0}, '{other_status:'h25b9df, wel:'h0, busy:'h0}, '{other_status:'h33fbe, wel:'h0, busy:'h0}}