9f4903e77a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_flash_and_tpm | 1.768m | 125.134ms | 0 | 50 | 0.00 |
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.470s | 41.559us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_device_csr_rw | 2.680s | 181.131us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 39.640s | 3.686ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_device_csr_aliasing | 17.430s | 16.575ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 3.800s | 55.310us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 2.680s | 181.131us | 20 | 20 | 100.00 |
| spi_device_csr_aliasing | 17.430s | 16.575ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_device_mem_walk | 0.690s | 17.024us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_device_mem_partial_access | 1.640s | 47.555us | 5 | 5 | 100.00 |
| V1 | TOTAL | 65 | 115 | 56.52 | |||
| V2 | csb_read | spi_device_csb_read | 0.870s | 24.053us | 50 | 50 | 100.00 |
| V2 | mem_parity | spi_device_mem_parity | 1.200s | 52.837us | 20 | 20 | 100.00 |
| V2 | mem_cfg | spi_device_ram_cfg | 0.750s | 16.009us | 1 | 1 | 100.00 |
| V2 | tpm_read | spi_device_tpm_rw | 11.520s | 270.717us | 50 | 50 | 100.00 |
| V2 | tpm_write | spi_device_tpm_rw | 11.520s | 270.717us | 50 | 50 | 100.00 |
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 36.370s | 51.874ms | 50 | 50 | 100.00 |
| spi_device_tpm_sts_read | 1.210s | 816.913us | 50 | 50 | 100.00 | ||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 1.069m | 70.206ms | 50 | 50 | 100.00 |
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 34.180s | 25.054ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 6.890s | 1.178ms | 0 | 50 | 0.00 | ||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 31.020s | 21.471ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 6.890s | 1.178ms | 0 | 50 | 0.00 | ||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 31.020s | 21.471ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 6.890s | 1.178ms | 0 | 50 | 0.00 | ||
| V2 | cmd_info_slots | spi_device_flash_all | 6.890s | 1.178ms | 0 | 50 | 0.00 |
| V2 | cmd_read_status | spi_device_intercept | 40.930s | 4.671ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 6.890s | 1.178ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_jedec | spi_device_intercept | 40.930s | 4.671ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 6.890s | 1.178ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_sfdp | spi_device_intercept | 40.930s | 4.671ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 6.890s | 1.178ms | 0 | 50 | 0.00 | ||
| V2 | cmd_fast_read | spi_device_intercept | 40.930s | 4.671ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 6.890s | 1.178ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_pipeline | spi_device_intercept | 40.930s | 4.671ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 6.890s | 1.178ms | 0 | 50 | 0.00 | ||
| V2 | flash_cmd_upload | spi_device_upload | 1.010m | 21.807ms | 39 | 50 | 78.00 |
| V2 | mailbox_command | spi_device_mailbox | 2.866m | 21.744ms | 46 | 50 | 92.00 |
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 2.866m | 21.744ms | 46 | 50 | 92.00 |
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 2.866m | 21.744ms | 46 | 50 | 92.00 |
| V2 | cmd_read_buffer | spi_device_flash_mode | 2.400m | 43.938ms | 46 | 50 | 92.00 |
| spi_device_read_buffer_direct | 19.230s | 4.565ms | 50 | 50 | 100.00 | ||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 2.866m | 21.744ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 6.890s | 1.178ms | 0 | 50 | 0.00 | ||
| V2 | quad_spi | spi_device_flash_all | 6.890s | 1.178ms | 0 | 50 | 0.00 |
| V2 | dual_spi | spi_device_flash_all | 6.890s | 1.178ms | 0 | 50 | 0.00 |
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 32.660s | 6.882ms | 20 | 50 | 40.00 |
| V2 | write_enable_disable | spi_device_cfg_cmd | 32.660s | 6.882ms | 20 | 50 | 40.00 |
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 1.768m | 125.134ms | 0 | 50 | 0.00 |
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 2.160m | 18.737ms | 0 | 50 | 0.00 |
| V2 | stress_all | spi_device_stress_all | 26.660s | 8.755ms | 13 | 50 | 26.00 |
| V2 | alert_test | spi_device_alert_test | 0.760s | 15.954us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_device_intr_test | 0.850s | 14.881us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 4.630s | 184.452us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_device_tl_errors | 4.630s | 184.452us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.470s | 41.559us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.680s | 181.131us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 17.430s | 16.575ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.090s | 394.930us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.470s | 41.559us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.680s | 181.131us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 17.430s | 16.575ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.090s | 394.930us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 771 | 961 | 80.23 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 1.130s | 1.162ms | 5 | 5 | 100.00 |
| spi_device_tl_intg_err | 23.810s | 832.935us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 23.810s | 832.935us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 861 | 1101 | 78.20 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 22 | 22 | 14 | 63.64 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 92.06 | 97.56 | 92.92 | 98.61 | 80.85 | 95.95 | 90.92 | 87.64 |
Job spi_device_2p-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 200 failures:
0.spi_device_cfg_cmd.11346254060851315100621086392823634014793259595509203840152389848665894853398
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_cfg_cmd/latest/run.log
Job ID: smart:b8c4553f-70d8-4d2f-9be7-00873f906879
1.spi_device_cfg_cmd.58834359148230762341972351860958440368752323949385576410879511987463745971897
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_cfg_cmd/latest/run.log
Job ID: smart:cddeac00-d93b-4349-bd5d-35718944338d
... and 19 more failures.
0.spi_device_flash_mode.41216929814109408357050112928426644918126450818926784017462750773607395175041
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_mode/latest/run.log
Job ID: smart:c4bc5c5d-9802-454f-896f-b4b652ce7c24
14.spi_device_flash_mode.84221603540051471250430675416925940918912341711090904905923178208518041929508
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_flash_mode/latest/run.log
Job ID: smart:61db8032-a226-481a-bf10-0e36f536b331
... and 2 more failures.
0.spi_device_flash_all.63128388742752450215616280432591106022290513416403289068390737666254441490095
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_all/latest/run.log
Job ID: smart:7427ea35-c8e0-44fe-99b0-07dbd1d14aa2
1.spi_device_flash_all.57204553408150113916785090557971641876113183252724635699500992363569571444929
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_all/latest/run.log
Job ID: smart:08b6b788-1233-4612-b4bb-7a5f2f73ddc9
... and 45 more failures.
0.spi_device_flash_and_tpm.107756341112582978904683358787815695445300877831475799155468044634563955874422
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:2249e019-e79f-4a76-acbf-a756caaf9158
1.spi_device_flash_and_tpm.114656875092817669614522569346047562726745067225956226708234879080792055834230
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:67cb3517-b9a9-433d-9759-c1d25a0155e1
... and 42 more failures.
0.spi_device_flash_and_tpm_min_idle.7983901104368733221404489014640562485372979984922668202967974892046051833342
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:e84e2f10-738a-4312-901f-6411fd0b0516
1.spi_device_flash_and_tpm_min_idle.28027448730616014398782485140448847221896373242069188291696735766913695764865
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:30a6963b-245d-4758-b936-8b924d048e0a
... and 39 more failures.
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 23 failures:
Test spi_device_upload has 6 failures.
2.spi_device_upload.76760480930601526033724555443607818559173247242321922505515334122330155533237
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_upload/latest/run.log
UVM_ERROR @ 6699881507 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 6701972438 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 6701972438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.spi_device_upload.114031842713369691950296719826352009681067630557347870576621520768941637781326
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_upload/latest/run.log
UVM_ERROR @ 1010395789 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 1010713955 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1010713955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_device_flash_and_tpm_min_idle has 4 failures.
5.spi_device_flash_and_tpm_min_idle.23524027245559596927368975120604034335522125733354030761665218682741242923609
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 963047090 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x142251) != exp '{'{other_status:'h50894, wel:'h0, busy:'h0}, '{other_status:'h50894, wel:'h0, busy:'h0}}
UVM_FATAL @ 970013042 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 970013042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.spi_device_flash_and_tpm_min_idle.39961634775006928629261341090333191285963423636601329546198462680165870751830
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 6054978468 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 6076773844 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 6076773844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_device_stress_all has 2 failures.
10.spi_device_stress_all.106442646738085673763653600125277224856980366827409638540108913133714366342310
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_stress_all/latest/run.log
UVM_ERROR @ 46920970 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 153102438 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 153102438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.spi_device_stress_all.50926811533832946841035703949729618964370494774284367068648598987938653409500
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_stress_all/latest/run.log
UVM_ERROR @ 8709268608 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x3267ab) != exp '{'{other_status:'hc99ea, wel:'h0, busy:'h0}, '{other_status:'hc99ea, wel:'h0, busy:'h0}}
UVM_FATAL @ 8754949535 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 8754949535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_flash_and_tpm has 3 failures.
13.spi_device_flash_and_tpm.60525710532010662398185838922924715804354092645573546769351601044863415208070
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 2052435366 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 2055690367 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2055690367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.spi_device_flash_and_tpm.41840041202610325075821098285806346116179080544325714730540880880238755805303
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/25.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 1196569150 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 1198069151 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1198069151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_device_cfg_cmd has 7 failures.
15.spi_device_cfg_cmd.48854022478230365795436978255692631914668485296847708381053789436962195541918
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 106345458 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8708ca) != exp '{'{other_status:'h21c232, wel:'h0, busy:'h0}, '{other_status:'h21c232, wel:'h0, busy:'h0}}
UVM_ERROR @ 106808602 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8708ca) != exp '{'{other_status:'h21c232, wel:'h0, busy:'h0}, '{other_status:'h21c232, wel:'h0, busy:'h0}}
UVM_ERROR @ 106882284 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8708ca) != exp '{'{other_status:'h21c232, wel:'h0, busy:'h0}, '{other_status:'h21c232, wel:'h0, busy:'h0}}
UVM_INFO @ 107408584 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 3, test op = 0xb7
UVM_ERROR @ 107734890 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8708ca) != exp '{'{other_status:'h21c232, wel:'h0, busy:'h0}, '{other_status:'h21c232, wel:'h0, busy:'h0}, '{other_status:'hb53ce, wel:'h0, busy:'h0}}
16.spi_device_cfg_cmd.38552434309848133439133958561458241990300226765200771925843847048688750447158
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 529084625 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x808af2) != exp '{'{other_status:'h2022bc, wel:'h0, busy:'h0}, '{other_status:'h2022bc, wel:'h0, busy:'h0}}
UVM_INFO @ 531584605 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 2, test op = 0xb7
UVM_ERROR @ 532120315 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x808af2) != exp '{'{other_status:'h2022bc, wel:'h0, busy:'h0}, '{other_status:'h2022bc, wel:'h0, busy:'h0}, '{other_status:'h1fcd6c, wel:'h0, busy:'h0}}
UVM_ERROR @ 533013165 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x808af2) != exp '{'{other_status:'h2022bc, wel:'h0, busy:'h0}, '{other_status:'h2022bc, wel:'h0, busy:'h0}, '{other_status:'h1fcd6c, wel:'h0, busy:'h0}}
UVM_ERROR @ 533513161 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x808af2) != exp '{'{other_status:'h2022bc, wel:'h0, busy:'h0}, '{other_status:'h2022bc, wel:'h0, busy:'h0}, '{other_status:'h1fcd6c, wel:'h0, busy:'h0}}
... and 5 more failures.
... and 1 more tests.
UVM_FATAL (spi_device_scoreboard.sv:726) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 11 failures:
Test spi_device_flash_all has 2 failures.
3.spi_device_flash_all.3492160250156530641716865194824678529383964724321388275534216852395694123522
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_flash_all/latest/run.log
UVM_FATAL @ 85045700 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 85045700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.spi_device_flash_all.108640312212389361475287037210126481647494326106604302547904932377278090953707
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_flash_all/latest/run.log
UVM_FATAL @ 287752033 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 287752033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_upload has 5 failures.
6.spi_device_upload.76797739557670835081140773865816387767418994807456179147471818199645596435151
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_upload/latest/run.log
UVM_FATAL @ 154820725 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 154820725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.spi_device_upload.58278231669925167734828006330488057949711803653546790816676862073500572623693
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_upload/latest/run.log
UVM_FATAL @ 4269803810 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 4269803810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test spi_device_flash_and_tpm_min_idle has 2 failures.
6.spi_device_flash_and_tpm_min_idle.5671266461123996280447066286150195502977703135986726544101533700895816198170
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 1633388953 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1633388953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.spi_device_flash_and_tpm_min_idle.27866307538549966352569780735781290532941120343047509880732492699081254413218
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 4553749744 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 4553749744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_flash_and_tpm has 2 failures.
18.spi_device_flash_and_tpm.57884736188793912999862919685851271433230059291581853305740968295653331443920
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 588091448 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 588091448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.spi_device_flash_and_tpm.37903375253699400397838123686850898190756297091558041653565989548858669135568
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 306128966 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 306128966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 3 failures:
Test spi_device_flash_and_tpm_min_idle has 2 failures.
21.spi_device_flash_and_tpm_min_idle.78890981960865252986289153085292521935784632097212336320364330961974228842039
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 61795392 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x74c80a) != exp '{'{other_status:'h1d3202, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h1d3202, wel:'h0, busy:'h0}, '{other_status:'h1d3202, wel:'h0, busy:'h0}}
UVM_FATAL @ 113638081 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 113638081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
45.spi_device_flash_and_tpm_min_idle.76775614740976659500313827364276654251878462013806276344184470858870887801736
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 11035191923 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xa64c36) != exp '{'{other_status:'h29930d, wel:'h0, busy:'h0}, '{other_status:'h2babaa, wel:'h0, busy:'h0}, '{other_status:'h29930d, wel:'h0, busy:'h0}, '{other_status:'h29930d, wel:'h0, busy:'h0}}
UVM_ERROR @ 13000553594 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xa64c36) != exp '{'{other_status:'h29930d, wel:'h0, busy:'h0}, '{other_status:'h2babaa, wel:'h0, busy:'h0}, '{other_status:'h29930d, wel:'h0, busy:'h0}, '{other_status:'h29930d, wel:'h0, busy:'h0}}
UVM_ERROR @ 16237732175 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xa64c36) != exp '{'{other_status:'h29930d, wel:'h0, busy:'h0}, '{other_status:'h2babaa, wel:'h0, busy:'h0}, '{other_status:'h29930d, wel:'h0, busy:'h0}, '{other_status:'h29930d, wel:'h0, busy:'h0}}
UVM_ERROR @ 16762004378 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xa64c36) != exp '{'{other_status:'h29930d, wel:'h0, busy:'h0}, '{other_status:'h2babaa, wel:'h0, busy:'h0}, '{other_status:'h29930d, wel:'h0, busy:'h0}, '{other_status:'h29930d, wel:'h0, busy:'h0}}
UVM_INFO @ 17897639606 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 2/10
Test spi_device_cfg_cmd has 1 failures.
26.spi_device_cfg_cmd.6918793741392314652306816109070852591674438293551904314143161461406994526090
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 703558301 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x57947a) != exp '{'{other_status:'h15e51e, wel:'h0, busy:'h0}, '{other_status:'h38ba4c, wel:'h0, busy:'h0}, '{other_status:'h15e51e, wel:'h0, busy:'h0}, '{other_status:'h15e51e, wel:'h0, busy:'h0}}
UVM_INFO @ 703864421 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 6, test op = 0xb7
UVM_ERROR @ 704068501 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x57947a) != exp '{'{other_status:'h15e51e, wel:'h0, busy:'h0}, '{other_status:'h38ba4c, wel:'h0, busy:'h0}, '{other_status:'h15e51e, wel:'h0, busy:'h0}, '{other_status:'h15e51e, wel:'h0, busy:'h0}}
UVM_ERROR @ 704354213 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x57947a) != exp '{'{other_status:'h15e51e, wel:'h0, busy:'h0}, '{other_status:'h38ba4c, wel:'h0, busy:'h0}, '{other_status:'h15e51e, wel:'h0, busy:'h0}, '{other_status:'h15e51e, wel:'h0, busy:'h0}}
UVM_ERROR @ 704782781 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x57947a) != exp '{'{other_status:'h15e51e, wel:'h0, busy:'h0}, '{other_status:'h38ba4c, wel:'h0, busy:'h0}, '{other_status:'h15e51e, wel:'h0, busy:'h0}, '{other_status:'h15e51e, wel:'h0, busy:'h0}}
UVM_ERROR (spi_device_scoreboard.sv:969) scoreboard [scoreboard] WEL mismatch: act=*, pred_fuzzy_q ('{}) pred=* has 1 failures:
14.spi_device_flash_and_tpm_min_idle.68441651640402543932954120187362183231559203927632758425303208547971769075379
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 6628406453 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR @ 6630073125 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR @ 6631739797 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR @ 6633406469 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR @ 6635073141 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR (spi_device_scoreboard.sv:969) scoreboard [scoreboard] WEL mismatch: act=*, pred_fuzzy_q ('{'{other_status:*, wel:*, busy:*}} ) pred=* has 1 failures:
23.spi_device_flash_and_tpm.8561902812698947377556613386778387229556769670879633246118575185957537509068
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 322803226 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h34cc1, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 322831002 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h34cc1, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 322858778 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h34cc1, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 322886554 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h34cc1, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 322914330 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h34cc1, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:
32.spi_device_cfg_cmd.106643680774356071831319526048226396255640593379499944139075981433301774232108
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/32.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 451693402 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x577476) != exp '{'{other_status:'h15dd1d, wel:'h0, busy:'h0}, '{other_status:'h15dd1d, wel:'h0, busy:'h0}, '{other_status:'hbf846, wel:'h0, busy:'h0}}
UVM_ERROR @ 451743907 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x577476) != exp '{'{other_status:'h15dd1d, wel:'h0, busy:'h0}, '{other_status:'h15dd1d, wel:'h0, busy:'h0}, '{other_status:'hbf846, wel:'h0, busy:'h0}}
UVM_ERROR @ 451915624 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2fe11a) != exp '{'{other_status:'h15dd1d, wel:'h0, busy:'h0}, '{other_status:'hbf846, wel:'h0, busy:'h0}, '{other_status:'hbf846, wel:'h0, busy:'h0}}
UVM_INFO @ 452127745 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 4, test op = 0xe9
UVM_ERROR @ 452299462 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2fe11a) != exp '{'{other_status:'h15dd1d, wel:'h0, busy:'h0}, '{other_status:'hbf846, wel:'h0, busy:'h0}, '{other_status:'hbf846, wel:'h0, busy:'h0}}