1c75f24e99| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_flash_and_tpm | 49.040s | 11.324ms | 0 | 50 | 0.00 |
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.480s | 41.505us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_device_csr_rw | 2.950s | 249.083us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 39.100s | 2.795ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_device_csr_aliasing | 25.310s | 1.233ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 4.070s | 490.748us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 2.950s | 249.083us | 20 | 20 | 100.00 |
| spi_device_csr_aliasing | 25.310s | 1.233ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_device_mem_walk | 0.700s | 14.292us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_device_mem_partial_access | 1.720s | 22.507us | 5 | 5 | 100.00 |
| V1 | TOTAL | 65 | 115 | 56.52 | |||
| V2 | csb_read | spi_device_csb_read | 0.870s | 57.202us | 50 | 50 | 100.00 |
| V2 | mem_parity | spi_device_mem_parity | 1.120s | 131.623us | 20 | 20 | 100.00 |
| V2 | mem_cfg | spi_device_ram_cfg | 0.740s | 17.587us | 1 | 1 | 100.00 |
| V2 | tpm_read | spi_device_tpm_rw | 16.540s | 356.421us | 50 | 50 | 100.00 |
| V2 | tpm_write | spi_device_tpm_rw | 16.540s | 356.421us | 50 | 50 | 100.00 |
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 31.760s | 11.961ms | 50 | 50 | 100.00 |
| spi_device_tpm_sts_read | 1.240s | 323.157us | 50 | 50 | 100.00 | ||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 1.075m | 11.484ms | 50 | 50 | 100.00 |
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 29.930s | 38.610ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 37.340s | 5.391ms | 1 | 50 | 2.00 | ||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 32.960s | 63.090ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 37.340s | 5.391ms | 1 | 50 | 2.00 | ||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 32.960s | 63.090ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 37.340s | 5.391ms | 1 | 50 | 2.00 | ||
| V2 | cmd_info_slots | spi_device_flash_all | 37.340s | 5.391ms | 1 | 50 | 2.00 |
| V2 | cmd_read_status | spi_device_intercept | 39.400s | 16.275ms | 43 | 50 | 86.00 |
| spi_device_flash_all | 37.340s | 5.391ms | 1 | 50 | 2.00 | ||
| V2 | cmd_read_jedec | spi_device_intercept | 39.400s | 16.275ms | 43 | 50 | 86.00 |
| spi_device_flash_all | 37.340s | 5.391ms | 1 | 50 | 2.00 | ||
| V2 | cmd_read_sfdp | spi_device_intercept | 39.400s | 16.275ms | 43 | 50 | 86.00 |
| spi_device_flash_all | 37.340s | 5.391ms | 1 | 50 | 2.00 | ||
| V2 | cmd_fast_read | spi_device_intercept | 39.400s | 16.275ms | 43 | 50 | 86.00 |
| spi_device_flash_all | 37.340s | 5.391ms | 1 | 50 | 2.00 | ||
| V2 | cmd_read_pipeline | spi_device_intercept | 39.400s | 16.275ms | 43 | 50 | 86.00 |
| spi_device_flash_all | 37.340s | 5.391ms | 1 | 50 | 2.00 | ||
| V2 | flash_cmd_upload | spi_device_upload | 33.890s | 40.058ms | 40 | 50 | 80.00 |
| V2 | mailbox_command | spi_device_mailbox | 3.126m | 21.041ms | 45 | 50 | 90.00 |
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 3.126m | 21.041ms | 45 | 50 | 90.00 |
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 3.126m | 21.041ms | 45 | 50 | 90.00 |
| V2 | cmd_read_buffer | spi_device_flash_mode | 2.762m | 48.217ms | 38 | 50 | 76.00 |
| spi_device_read_buffer_direct | 22.180s | 4.364ms | 50 | 50 | 100.00 | ||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 3.126m | 21.041ms | 45 | 50 | 90.00 |
| spi_device_flash_all | 37.340s | 5.391ms | 1 | 50 | 2.00 | ||
| V2 | quad_spi | spi_device_flash_all | 37.340s | 5.391ms | 1 | 50 | 2.00 |
| V2 | dual_spi | spi_device_flash_all | 37.340s | 5.391ms | 1 | 50 | 2.00 |
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 32.810s | 3.291ms | 22 | 50 | 44.00 |
| V2 | write_enable_disable | spi_device_cfg_cmd | 32.810s | 3.291ms | 22 | 50 | 44.00 |
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 49.040s | 11.324ms | 0 | 50 | 0.00 |
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 1.275m | 39.319ms | 0 | 50 | 0.00 |
| V2 | stress_all | spi_device_stress_all | 28.340s | 10.987ms | 14 | 50 | 28.00 |
| V2 | alert_test | spi_device_alert_test | 0.790s | 16.300us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_device_intr_test | 0.820s | 12.256us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 6.110s | 210.737us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_device_tl_errors | 6.110s | 210.737us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.480s | 41.505us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.950s | 249.083us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 25.310s | 1.233ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.130s | 166.209us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.480s | 41.505us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.950s | 249.083us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 25.310s | 1.233ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.130s | 166.209us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 764 | 961 | 79.50 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 1.230s | 330.870us | 5 | 5 | 100.00 |
| spi_device_tl_intg_err | 22.910s | 3.347ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 22.910s | 3.347ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 854 | 1101 | 77.57 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 22 | 22 | 14 | 63.64 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.99 | 97.56 | 92.93 | 98.61 | 80.85 | 95.95 | 90.92 | 87.09 |
Job spi_device_2p-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 209 failures:
0.spi_device_flash_all.100053103970132742581284248703948075546840112304783448051261052423454139996963
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_all/latest/run.log
Job ID: smart:72974610-97fe-4485-8f10-1985429edfe4
1.spi_device_flash_all.76831126049436703787830566875921285695505701228283706936941454267606955054251
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_all/latest/run.log
Job ID: smart:175379f4-f6d1-40a7-bdeb-05fd48b17d52
... and 40 more failures.
0.spi_device_flash_and_tpm.93913039522407423512076897211872548434780671143992776301117264837107356159228
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:bb52caa3-2a45-4970-9ac8-2fcfd5c50d91
1.spi_device_flash_and_tpm.51982398863032438735933527004893810154368939846336986148679599426630885220551
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:c1e99cba-5408-4b1e-8ba9-0b1006f76cb2
... and 45 more failures.
0.spi_device_flash_and_tpm_min_idle.44422753373229535133922908102876332791559064771987422497365414315732402252416
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:775f84c3-407e-456c-9a5d-ee3fba8f64ce
1.spi_device_flash_and_tpm_min_idle.21828817601688292987933217313007207574717991442434228608428805228695716641182
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:9b657101-672a-49ba-a352-cc9819b391e4
... and 44 more failures.
0.spi_device_stress_all.52730076538966844903764083934971885508120530412993753478151665971553374270613
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_stress_all/latest/run.log
Job ID: smart:df195787-8905-4cf7-940d-33c2eacdd6cf
1.spi_device_stress_all.88934219815875093748839832640438344236505811197716242295891492011566212412860
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_stress_all/latest/run.log
Job ID: smart:3ed0667f-427a-4569-bc62-65530f0804cc
... and 30 more failures.
1.spi_device_intercept.18615753497988095458214221199450507886324876998810747901327783741814749771371
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_intercept/latest/run.log
Job ID: smart:e1dfa66a-e4a2-4405-aa26-399b03881068
3.spi_device_intercept.20192479483767577030173428833640220417719094945694218495811050123067554291802
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_intercept/latest/run.log
Job ID: smart:8d6a16b7-446f-4489-b043-98309392c25d
... and 5 more failures.
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 19 failures:
Test spi_device_cfg_cmd has 6 failures.
3.spi_device_cfg_cmd.97401316921646958393807515597026933958915294583292412443598209114943888473801
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 106276727 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 108752915 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 111229103 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 1, test op = 0xe9
UVM_ERROR @ 111895769 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h2f0639, wel:'h0, busy:'h0}}
UVM_ERROR @ 112943387 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h2f0639, wel:'h0, busy:'h0}}
4.spi_device_cfg_cmd.33825540126171552641110952129164744189683326323106298888812943563371686217434
Line 258, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 577406558 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1fcde6) != exp '{'{other_status:'h7f379, wel:'h0, busy:'h0}, '{other_status:'h7f379, wel:'h0, busy:'h0}}
UVM_ERROR @ 577698220 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1fcde6) != exp '{'{other_status:'h7f379, wel:'h0, busy:'h0}, '{other_status:'h7f379, wel:'h0, busy:'h0}}
UVM_ERROR @ 578510707 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1fcde6) != exp '{'{other_status:'h7f379, wel:'h0, busy:'h0}, '{other_status:'h7f379, wel:'h0, busy:'h0}}
UVM_ERROR @ 579198196 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1fcde6) != exp '{'{other_status:'h7f379, wel:'h0, busy:'h0}, '{other_status:'h7f379, wel:'h0, busy:'h0}}
UVM_INFO @ 579469025 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 9, test op = 0xe9
... and 4 more failures.
Test spi_device_upload has 6 failures.
11.spi_device_upload.67983459305574124670404098303523136634910165891164444162931522294420764165139
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_upload/latest/run.log
UVM_ERROR @ 208834703 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 214074703 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 216631703 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 1, test op = 0x76
UVM_INFO @ 218573703 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 2, test op = 0xd0
UVM_ERROR @ 222674703 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
18.spi_device_upload.86833372093612095026236827332964721014228612535154804075295964274418842041196
Line 262, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_upload/latest/run.log
UVM_ERROR @ 2219595094 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 2227261753 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 2230526998 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 13, test op = 0x65
UVM_INFO @ 2263019293 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 14, test op = 0xcf
UVM_INFO @ 2571449768 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 15, test op = 0x6b
... and 4 more failures.
Test spi_device_stress_all has 2 failures.
11.spi_device_stress_all.107119363728725965638736760616520047636116593573257588222290842217295948924856
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_stress_all/latest/run.log
UVM_ERROR @ 1257355949 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x72fb81) != exp '{'{other_status:'h1cbee0, wel:'h0, busy:'h0}, '{other_status:'h1cbee0, wel:'h0, busy:'h0}}
UVM_FATAL @ 1261332340 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1261332340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.spi_device_stress_all.57664679331409949244791466596423999625033017543989991517585473629811860961856
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_stress_all/latest/run.log
UVM_ERROR @ 10980027774 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc54a75) != exp '{'{other_status:'h31529d, wel:'h0, busy:'h0}, '{other_status:'h31529d, wel:'h0, busy:'h0}}
UVM_FATAL @ 10986503748 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 10986503748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_flash_and_tpm_min_idle has 2 failures.
14.spi_device_flash_and_tpm_min_idle.12590386667486454900376684098779487899882229324757917222750870228867134579191
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 2725647069 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 2728649145 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2728649145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.spi_device_flash_and_tpm_min_idle.44341943724605784018783827308465909005575598954982039370710844027053407356833
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 7655905666 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x9c4b92) != exp '{'{other_status:'h2712e4, wel:'h0, busy:'h0}, '{other_status:'h2712e4, wel:'h0, busy:'h0}}
UVM_ERROR @ 15516690774 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x9c4b92) != exp '{'{other_status:'h2712e4, wel:'h0, busy:'h0}, '{other_status:'h2712e4, wel:'h0, busy:'h0}}
UVM_INFO @ 28167250836 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 1/15
UVM_INFO @ 38106702576 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 2/15
UVM_INFO @ 39009878718 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 2/13
Test spi_device_flash_and_tpm has 2 failures.
31.spi_device_flash_and_tpm.67598221814253355290519239110041612058188629717839568287232341003573481571258
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 1445999952 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 1827785510 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/17
UVM_INFO @ 2423192650 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/17
UVM_INFO @ 2974038003 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 4/17
UVM_INFO @ 3525820841 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 5/17
35.spi_device_flash_and_tpm.15338964232825844905273587363233773696988653642462043664507112194047584196529
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 199855805 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 401742273 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR @ 402075601 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR @ 402408929 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR @ 402742257 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
... and 1 more tests.
UVM_FATAL (spi_device_scoreboard.sv:726) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 15 failures:
Test spi_device_flash_and_tpm_min_idle has 2 failures.
2.spi_device_flash_and_tpm_min_idle.96341926182610230401120509034769112701384979458617356417300692950719205396439
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 1263878939 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1263878939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.spi_device_flash_and_tpm_min_idle.88867801736898312998862337915872011363238279760365793360315997559567695497012
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/27.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 504798324 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 504798324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_flash_all has 6 failures.
5.spi_device_flash_all.114990249821553486376924246590490891664631454940326601185654580173705123539487
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_flash_all/latest/run.log
UVM_FATAL @ 6102690565 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 6102690565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.spi_device_flash_all.7810767851787656163768246916855245273686889761744971012672913903091566705566
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_flash_all/latest/run.log
UVM_FATAL @ 3618046923 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 3618046923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_device_flash_and_tpm has 1 failures.
8.spi_device_flash_and_tpm.103294899550330486328651517306040761182963351328694857520228087053912121432803
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 390323414 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 390323414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_upload has 4 failures.
16.spi_device_upload.110266750721497150276788195545005398509695280185068562138479207402255074941764
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_upload/latest/run.log
UVM_FATAL @ 12751640173 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 12751640173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.spi_device_upload.38773028247534745477141125537030329126597930634952727594458682051742491601221
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/30.spi_device_upload/latest/run.log
UVM_FATAL @ 26754543 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 26754543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_device_stress_all has 2 failures.
24.spi_device_stress_all.90848769214358500788262065856579119957372194418802057318874913390206350836216
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_stress_all/latest/run.log
UVM_FATAL @ 34572798 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 34572798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.spi_device_stress_all.28396838676716076200987318260814760737082307254892608291965064193065836118893
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/30.spi_device_stress_all/latest/run.log
UVM_FATAL @ 154106920 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 154106920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 2 failures:
13.spi_device_cfg_cmd.69179502112975448566694938103938076376708285391109575888956286061076428249139
Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 1344870189 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xcdc046) != exp '{'{other_status:'h337011, wel:'h0, busy:'h0}, '{other_status:'h791ec, wel:'h0, busy:'h0}, '{other_status:'h337011, wel:'h0, busy:'h0}, '{other_status:'h337011, wel:'h0, busy:'h0}}
UVM_ERROR @ 1446727230 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xcdc046) != exp '{'{other_status:'h337011, wel:'h0, busy:'h0}, '{other_status:'h791ec, wel:'h0, busy:'h0}, '{other_status:'h337011, wel:'h0, busy:'h0}, '{other_status:'h337011, wel:'h0, busy:'h0}}
UVM_INFO @ 1451727230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.spi_device_cfg_cmd.27861418761505841412656684955125966367424098786458445136207151076823564835169
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 196642536 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xbea0e6) != exp '{'{other_status:'h2b17fb, wel:'h0, busy:'h0}, '{other_status:'h2fa839, wel:'h0, busy:'h0}, '{other_status:'h40f1e, wel:'h0, busy:'h0}, '{other_status:'h40f1e, wel:'h0, busy:'h0}}
UVM_INFO @ 196767540 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 5, test op = 0xb7
UVM_ERROR @ 197319641 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xbea0e6) != exp '{'{other_status:'h2b17fb, wel:'h0, busy:'h0}, '{other_status:'h2fa839, wel:'h0, busy:'h0}, '{other_status:'h40f1e, wel:'h0, busy:'h0}, '{other_status:'h40f1e, wel:'h0, busy:'h0}}
UVM_ERROR @ 197444645 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xbea0e6) != exp '{'{other_status:'h2b17fb, wel:'h0, busy:'h0}, '{other_status:'h2fa839, wel:'h0, busy:'h0}, '{other_status:'h40f1e, wel:'h0, busy:'h0}, '{other_status:'h40f1e, wel:'h0, busy:'h0}}
UVM_ERROR @ 197475896 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xbea0e6) != exp '{'{other_status:'h2b17fb, wel:'h0, busy:'h0}, '{other_status:'h2fa839, wel:'h0, busy:'h0}, '{other_status:'h40f1e, wel:'h0, busy:'h0}, '{other_status:'h40f1e, wel:'h0, busy:'h0}}
UVM_FATAL (spi_device_scoreboard.sv:1124) [scoreboard] timeout occurred! has 1 failures:
4.spi_device_flash_mode.58890843746157651489803116484339360579228238060832781505404197053884821966804
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_flash_mode/latest/run.log
UVM_FATAL @ 106916726056 ps: (spi_device_scoreboard.sv:1124) [uvm_test_top.env.scoreboard] timeout occurred!
UVM_INFO @ 106916726056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:
31.spi_device_cfg_cmd.34097675775451093438621083417111975122341741591621562516957008849036693324104
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 4430086768 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x64a0e2) != exp '{'{other_status:'h192838, wel:'h0, busy:'h0}, '{other_status:'hd25d5, wel:'h0, busy:'h0}, '{other_status:'hd25d5, wel:'h0, busy:'h0}}
UVM_ERROR @ 4435420112 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x64a0e2) != exp '{'{other_status:'h192838, wel:'h0, busy:'h0}, '{other_status:'hd25d5, wel:'h0, busy:'h0}, '{other_status:'hd25d5, wel:'h0, busy:'h0}}
UVM_INFO @ 4445753466 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 2, test op = 0x4
UVM_ERROR @ 4448420138 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x349756) != exp '{'{other_status:'hd25d5, wel:'h0, busy:'h0}, '{other_status:'h192838, wel:'h0, busy:'h0}, '{other_status:'hd25d5, wel:'h0, busy:'h0}, '{other_status:'hd25d5, wel:'h0, busy:'h0}}
UVM_ERROR @ 4449420140 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x349756) != exp '{'{other_status:'hd25d5, wel:'h0, busy:'h0}, '{other_status:'h192838, wel:'h0, busy:'h0}, '{other_status:'hd25d5, wel:'h0, busy:'h0}, '{other_status:'hd25d5, wel:'h0, busy:'h0}}