SPI_DEVICE/2P Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: d3942ca074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 57.930s 25.160ms 0 50 0.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.410s 58.416us 5 5 100.00
V1 csr_rw spi_device_csr_rw 2.410s 86.382us 20 20 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 38.980s 2.719ms 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 23.540s 1.157ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 4.050s 57.925us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.410s 86.382us 20 20 100.00
spi_device_csr_aliasing 23.540s 1.157ms 5 5 100.00
V1 mem_walk spi_device_mem_walk 0.650s 20.944us 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 2.080s 57.023us 5 5 100.00
V1 TOTAL 65 115 56.52
V2 csb_read spi_device_csb_read 0.900s 41.611us 50 50 100.00
V2 mem_parity spi_device_mem_parity 1.130s 34.894us 20 20 100.00
V2 mem_cfg spi_device_ram_cfg 0.700s 39.772us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 12.300s 325.998us 50 50 100.00
V2 tpm_write spi_device_tpm_rw 12.300s 325.998us 50 50 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 28.060s 32.624ms 50 50 100.00
spi_device_tpm_sts_read 1.220s 1.186ms 50 50 100.00
V2 tpm_fully_random_case spi_device_tpm_all 52.970s 88.991ms 50 50 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 1.070m 27.264ms 50 50 100.00
spi_device_flash_all 35.420s 11.647ms 0 50 0.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 57.520s 84.735ms 50 50 100.00
spi_device_flash_all 35.420s 11.647ms 0 50 0.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 57.520s 84.735ms 50 50 100.00
spi_device_flash_all 35.420s 11.647ms 0 50 0.00
V2 cmd_info_slots spi_device_flash_all 35.420s 11.647ms 0 50 0.00
V2 cmd_read_status spi_device_intercept 53.650s 6.186ms 40 50 80.00
spi_device_flash_all 35.420s 11.647ms 0 50 0.00
V2 cmd_read_jedec spi_device_intercept 53.650s 6.186ms 40 50 80.00
spi_device_flash_all 35.420s 11.647ms 0 50 0.00
V2 cmd_read_sfdp spi_device_intercept 53.650s 6.186ms 40 50 80.00
spi_device_flash_all 35.420s 11.647ms 0 50 0.00
V2 cmd_fast_read spi_device_intercept 53.650s 6.186ms 40 50 80.00
spi_device_flash_all 35.420s 11.647ms 0 50 0.00
V2 cmd_read_pipeline spi_device_intercept 53.650s 6.186ms 40 50 80.00
spi_device_flash_all 35.420s 11.647ms 0 50 0.00
V2 flash_cmd_upload spi_device_upload 32.270s 11.265ms 41 50 82.00
V2 mailbox_command spi_device_mailbox 2.425m 86.197ms 45 50 90.00
V2 mailbox_cross_outside_command spi_device_mailbox 2.425m 86.197ms 45 50 90.00
V2 mailbox_cross_inside_command spi_device_mailbox 2.425m 86.197ms 45 50 90.00
V2 cmd_read_buffer spi_device_flash_mode 2.592m 21.045ms 42 50 84.00
spi_device_read_buffer_direct 20.520s 9.968ms 50 50 100.00
V2 cmd_dummy_cycle spi_device_mailbox 2.425m 86.197ms 45 50 90.00
spi_device_flash_all 35.420s 11.647ms 0 50 0.00
V2 quad_spi spi_device_flash_all 35.420s 11.647ms 0 50 0.00
V2 dual_spi spi_device_flash_all 35.420s 11.647ms 0 50 0.00
V2 4b_3b_feature spi_device_cfg_cmd 14.980s 3.845ms 21 50 42.00
V2 write_enable_disable spi_device_cfg_cmd 14.980s 3.845ms 21 50 42.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 57.930s 25.160ms 0 50 0.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 41.310s 4.859ms 0 50 0.00
V2 stress_all spi_device_stress_all 1.844m 17.317ms 11 50 22.00
V2 alert_test spi_device_alert_test 0.790s 129.162us 50 50 100.00
V2 intr_test spi_device_intr_test 0.770s 66.085us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 5.270s 685.970us 20 20 100.00
V2 tl_d_illegal_access spi_device_tl_errors 5.270s 685.970us 20 20 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.410s 58.416us 5 5 100.00
spi_device_csr_rw 2.410s 86.382us 20 20 100.00
spi_device_csr_aliasing 23.540s 1.157ms 5 5 100.00
spi_device_same_csr_outstanding 4.640s 840.321us 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.410s 58.416us 5 5 100.00
spi_device_csr_rw 2.410s 86.382us 20 20 100.00
spi_device_csr_aliasing 23.540s 1.157ms 5 5 100.00
spi_device_same_csr_outstanding 4.640s 840.321us 20 20 100.00
V2 TOTAL 761 961 79.19
V2S tl_intg_err spi_device_sec_cm 1.180s 1.632ms 5 5 100.00
spi_device_tl_intg_err 24.340s 5.993ms 20 20 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 24.340s 5.993ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 851 1101 77.29

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 22 22 14 63.64
V2S 2 2 2 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
92.11 97.56 92.92 98.61 80.85 95.95 90.92 87.98

Failure Buckets

Past Results