4fd94db59a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_flash_and_tpm | 4.090s | 180.042us | 0 | 50 | 0.00 |
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.350s | 23.550us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_device_csr_rw | 3.090s | 243.652us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 40.480s | 5.523ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_device_csr_aliasing | 23.400s | 1.097ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 3.760s | 542.984us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 3.090s | 243.652us | 20 | 20 | 100.00 |
| spi_device_csr_aliasing | 23.400s | 1.097ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_device_mem_walk | 0.670s | 25.855us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_device_mem_partial_access | 1.900s | 42.631us | 5 | 5 | 100.00 |
| V1 | TOTAL | 65 | 115 | 56.52 | |||
| V2 | csb_read | spi_device_csb_read | 0.840s | 19.391us | 50 | 50 | 100.00 |
| V2 | mem_parity | spi_device_mem_parity | 1.130s | 209.648us | 20 | 20 | 100.00 |
| V2 | mem_cfg | spi_device_ram_cfg | 0.710s | 16.991us | 1 | 1 | 100.00 |
| V2 | tpm_read | spi_device_tpm_rw | 18.690s | 7.896ms | 50 | 50 | 100.00 |
| V2 | tpm_write | spi_device_tpm_rw | 18.690s | 7.896ms | 50 | 50 | 100.00 |
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 30.740s | 13.551ms | 50 | 50 | 100.00 |
| spi_device_tpm_sts_read | 1.180s | 179.219us | 50 | 50 | 100.00 | ||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 1.075m | 55.761ms | 50 | 50 | 100.00 |
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 49.240s | 70.222ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 46.880s | 42.490ms | 0 | 50 | 0.00 | ||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 52.540s | 85.440ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 46.880s | 42.490ms | 0 | 50 | 0.00 | ||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 52.540s | 85.440ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 46.880s | 42.490ms | 0 | 50 | 0.00 | ||
| V2 | cmd_info_slots | spi_device_flash_all | 46.880s | 42.490ms | 0 | 50 | 0.00 |
| V2 | cmd_read_status | spi_device_intercept | 42.910s | 11.061ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 46.880s | 42.490ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_jedec | spi_device_intercept | 42.910s | 11.061ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 46.880s | 42.490ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_sfdp | spi_device_intercept | 42.910s | 11.061ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 46.880s | 42.490ms | 0 | 50 | 0.00 | ||
| V2 | cmd_fast_read | spi_device_intercept | 42.910s | 11.061ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 46.880s | 42.490ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_pipeline | spi_device_intercept | 42.910s | 11.061ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 46.880s | 42.490ms | 0 | 50 | 0.00 | ||
| V2 | flash_cmd_upload | spi_device_upload | 51.860s | 32.714ms | 36 | 50 | 72.00 |
| V2 | mailbox_command | spi_device_mailbox | 3.061m | 16.466ms | 45 | 50 | 90.00 |
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 3.061m | 16.466ms | 45 | 50 | 90.00 |
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 3.061m | 16.466ms | 45 | 50 | 90.00 |
| V2 | cmd_read_buffer | spi_device_flash_mode | 3.002m | 54.592ms | 41 | 50 | 82.00 |
| spi_device_read_buffer_direct | 19.730s | 1.302ms | 50 | 50 | 100.00 | ||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 3.061m | 16.466ms | 45 | 50 | 90.00 |
| spi_device_flash_all | 46.880s | 42.490ms | 0 | 50 | 0.00 | ||
| V2 | quad_spi | spi_device_flash_all | 46.880s | 42.490ms | 0 | 50 | 0.00 |
| V2 | dual_spi | spi_device_flash_all | 46.880s | 42.490ms | 0 | 50 | 0.00 |
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 20.720s | 2.235ms | 18 | 50 | 36.00 |
| V2 | write_enable_disable | spi_device_cfg_cmd | 20.720s | 2.235ms | 18 | 50 | 36.00 |
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 4.090s | 180.042us | 0 | 50 | 0.00 |
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 54.350s | 6.310ms | 1 | 50 | 2.00 |
| V2 | stress_all | spi_device_stress_all | 9.540s | 1.693ms | 12 | 50 | 24.00 |
| V2 | alert_test | spi_device_alert_test | 0.780s | 21.999us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_device_intr_test | 0.820s | 28.027us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 4.890s | 212.325us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_device_tl_errors | 4.890s | 212.325us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.350s | 23.550us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 3.090s | 243.652us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 23.400s | 1.097ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.010s | 347.601us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.350s | 23.550us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 3.090s | 243.652us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 23.400s | 1.097ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.010s | 347.601us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 760 | 961 | 79.08 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 1.440s | 1.086ms | 5 | 5 | 100.00 |
| spi_device_tl_intg_err | 22.880s | 2.061ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 22.880s | 2.061ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 850 | 1101 | 77.20 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 22 | 22 | 14 | 63.64 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 92.18 | 97.56 | 92.91 | 98.61 | 80.85 | 95.97 | 90.92 | 88.43 |
Job spi_device_2p-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 214 failures:
0.spi_device_mailbox.33770074734105169995888929900224540477076165744428695428478269862737911281997
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_mailbox/latest/run.log
Job ID: smart:ccc28582-c863-43e3-84d7-f5792fba369c
2.spi_device_mailbox.102607063064457293394085164390386674528997805250983396917243875479078771621341
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_mailbox/latest/run.log
Job ID: smart:9f6b2bad-b2f2-4969-aee8-5224e257d289
... and 3 more failures.
0.spi_device_flash_all.7758598817371171750851252366021427656759100227234040246372479455978499854060
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_all/latest/run.log
Job ID: smart:7902982a-6573-4be6-9824-4c6f49f3ff8d
1.spi_device_flash_all.25812512405164742584974569427658540408565636884434248907805912201413238649817
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_all/latest/run.log
Job ID: smart:88f07a5d-433f-46df-9b0b-92c497f8e514
... and 40 more failures.
0.spi_device_flash_and_tpm.88563740570730641922836486265004307002462486287504797683589555896234331140120
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:aacef3bb-32d7-460b-92c5-87fbbaf4c1cb
1.spi_device_flash_and_tpm.113640723760571627183324740640632291997867901749264886259146134902198460015285
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:495aca40-d4ba-42b1-869a-adba1617cead
... and 47 more failures.
0.spi_device_flash_and_tpm_min_idle.98286660547390687442589052335780270815696938918870307991919291171815030658504
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:b487b9eb-3c94-4701-b91f-d0c786930d7a
1.spi_device_flash_and_tpm_min_idle.104416409562950745800363787680240120493695522881157648469635236711584795397583
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:d2acc999-71c5-46b7-85f1-ce9ed1ac5552
... and 43 more failures.
1.spi_device_cfg_cmd.105314545628002997609726039987497312692018528750947413454356182053492085044076
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_cfg_cmd/latest/run.log
Job ID: smart:1cd428ff-0d6e-4774-8466-588b8a49a6e4
3.spi_device_cfg_cmd.77232849873577409047309788372200441382740615125935228701250474796307615689102
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_cfg_cmd/latest/run.log
Job ID: smart:c0408ba8-c495-4796-ab1b-81c2a331285d
... and 23 more failures.
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 26 failures:
Test spi_device_upload has 13 failures.
0.spi_device_upload.67776540561313990867023857725211357388265395667776597549744679998100509898177
Line 268, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_upload/latest/run.log
UVM_ERROR @ 14257016815 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 14265150616 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 14267139464 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 19, test op = 0x4b
UVM_INFO @ 14896401748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.spi_device_upload.3907433320877939565906683403658286685576131944607954924534999601611929504542
Line 258, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_upload/latest/run.log
UVM_ERROR @ 788588606 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 790557419 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 791128044 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 9, test op = 0x9f
UVM_INFO @ 856621873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
Test spi_device_flash_all has 4 failures.
3.spi_device_flash_all.18590186319534573835319258017588978357475114118031772105008451206983729033761
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_flash_all/latest/run.log
UVM_ERROR @ 88716786 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 620426786 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h4a708, wel:'h0, busy:'h0}} ) pred=0x0
UVM_FATAL @ 620436787 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 620436787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.spi_device_flash_all.30094830817387109421401294941998473724254625216705064834802184224807978145827
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_flash_all/latest/run.log
UVM_ERROR @ 407609897 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x3) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 2811379127 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 3570760202 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x241ce2) != exp '{'{other_status:'h90738, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h90738, wel:'h0, busy:'h0}, '{other_status:'h90738, wel:'h0, busy:'h0}}
UVM_INFO @ 4745310856 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 1/5
UVM_ERROR @ 5079730606 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h90738, wel:'h0, busy:'h0}} ) pred=0x0
... and 2 more failures.
Test spi_device_cfg_cmd has 7 failures.
10.spi_device_cfg_cmd.43110590628351827629586364866123642690300065380600332889334776740722240603763
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 175663728 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x3acfba) != exp '{'{other_status:'heb3ee, wel:'h0, busy:'h0}, '{other_status:'heb3ee, wel:'h0, busy:'h0}}
UVM_ERROR @ 176580380 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x3acfba) != exp '{'{other_status:'heb3ee, wel:'h0, busy:'h0}, '{other_status:'heb3ee, wel:'h0, busy:'h0}}
UVM_INFO @ 176934541 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 3, test op = 0xb7
UVM_ERROR @ 177372034 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x3acfba) != exp '{'{other_status:'heb3ee, wel:'h0, busy:'h0}, '{other_status:'heb3ee, wel:'h0, busy:'h0}}
UVM_ERROR @ 177413700 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x3acfba) != exp '{'{other_status:'heb3ee, wel:'h0, busy:'h0}, '{other_status:'heb3ee, wel:'h0, busy:'h0}}
12.spi_device_cfg_cmd.45547967118553252921009048959901456355415747418358004354881924881538149450382
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 2739001812 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x917cbe) != exp '{'{other_status:'h245f2f, wel:'h0, busy:'h0}, '{other_status:'h245f2f, wel:'h0, busy:'h0}}
UVM_ERROR @ 2741361812 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x917cbe) != exp '{'{other_status:'h245f2f, wel:'h0, busy:'h0}, '{other_status:'h245f2f, wel:'h0, busy:'h0}}
UVM_ERROR @ 2741841812 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x917cbe) != exp '{'{other_status:'h245f2f, wel:'h0, busy:'h0}, '{other_status:'h245f2f, wel:'h0, busy:'h0}}
UVM_ERROR @ 2742281812 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x917cbe) != exp '{'{other_status:'h245f2f, wel:'h0, busy:'h0}, '{other_status:'h245f2f, wel:'h0, busy:'h0}}
UVM_ERROR @ 2743361812 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x917cbe) != exp '{'{other_status:'h245f2f, wel:'h0, busy:'h0}, '{other_status:'h245f2f, wel:'h0, busy:'h0}}
... and 5 more failures.
Test spi_device_stress_all has 1 failures.
24.spi_device_stress_all.16631367979608558326188729152628031056908025599880271583643800330158177793667
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_stress_all/latest/run.log
UVM_ERROR @ 407247984 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xda0889) != exp '{'{other_status:'h368222, wel:'h0, busy:'h0}, '{other_status:'h368222, wel:'h0, busy:'h0}}
UVM_ERROR @ 785049873 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xd8114e) != exp '{'{other_status:'h360453, wel:'h0, busy:'h0}, '{other_status:'h360453, wel:'h0, busy:'h0}}
UVM_ERROR @ 912517177 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xac2faa) != exp '{'{other_status:'h360453, wel:'h0, busy:'h0}, '{other_status:'h2b0bea, wel:'h0, busy:'h0}, '{other_status:'h2b0bea, wel:'h0, busy:'h0}}
UVM_ERROR @ 936650631 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xac2faa) != exp '{'{other_status:'h2b0bea, wel:'h0, busy:'h0}, '{other_status:'h360453, wel:'h0, busy:'h0}, '{other_status:'h2b0bea, wel:'h0, busy:'h0}, '{other_status:'h2b0bea, wel:'h0, busy:'h0}}
UVM_INFO @ 1015618258 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 1/7
Test spi_device_flash_and_tpm has 1 failures.
48.spi_device_flash_and_tpm.91331923098285548349684266184118518117194924442180356420485084426469150706990
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/48.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 161028468 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 180042465 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 180042465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (spi_device_scoreboard.sv:726) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 10 failures:
Test spi_device_stress_all has 2 failures.
0.spi_device_stress_all.72307463538850531743358393009971862111564330388873181398804893355784668013097
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_stress_all/latest/run.log
UVM_FATAL @ 406083522 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 406083522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.spi_device_stress_all.102320161439922749807740792481765639612749806703100517232981584180091801029688
Line 260, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_stress_all/latest/run.log
UVM_FATAL @ 610372561 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 610372561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_upload has 1 failures.
23.spi_device_upload.94167051035966917714748579130007560959249702164740238345415354147946883427555
Line 265, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_upload/latest/run.log
UVM_FATAL @ 28258410213 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 28258410213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_flash_all has 4 failures.
28.spi_device_flash_all.103231555051883745111692715506830722164527378378703712437537969054696958321491
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/28.spi_device_flash_all/latest/run.log
UVM_FATAL @ 267024272 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 267024272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.spi_device_flash_all.112954028980915832473789408957055303237750474911346409756849151623466906904496
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_flash_all/latest/run.log
UVM_FATAL @ 3097917862 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 3097917862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_device_flash_and_tpm_min_idle has 3 failures.
43.spi_device_flash_and_tpm_min_idle.5268300685797602493848090780341705027214854826366237623542767602148798740577
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 865970621 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 865970621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
44.spi_device_flash_and_tpm_min_idle.86046042950417828312219234644604159598083012315158045057099925146746016159406
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/44.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 599493350 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 599493350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:
33.spi_device_flash_and_tpm_min_idle.86680926995250708794722700549013522072381130592548516265543449559707206105721
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/33.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 3522501578 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h324946, wel:'h0, busy:'h0}}
UVM_ERROR @ 18915022504 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc9251a) != exp '{'{other_status:'h324946, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h324946, wel:'h0, busy:'h0}, '{other_status:'h324946, wel:'h0, busy:'h0}}
UVM_ERROR @ 23092190424 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc9251a) != exp '{'{other_status:'h324946, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h324946, wel:'h0, busy:'h0}, '{other_status:'h324946, wel:'h0, busy:'h0}}
UVM_ERROR @ 24342340782 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc9251a) != exp '{'{other_status:'h324946, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h324946, wel:'h0, busy:'h0}, '{other_status:'h324946, wel:'h0, busy:'h0}}
UVM_ERROR @ 24627342492 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc9251a) != exp '{'{other_status:'h324946, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h324946, wel:'h0, busy:'h0}, '{other_status:'h324946, wel:'h0, busy:'h0}}