41bc3e0c7f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_flash_and_tpm | 16.790s | 1.464ms | 0 | 50 | 0.00 |
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.230s | 60.865us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_device_csr_rw | 2.890s | 125.798us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 36.620s | 4.347ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_device_csr_aliasing | 23.280s | 1.812ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 4.230s | 120.226us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 2.890s | 125.798us | 20 | 20 | 100.00 |
| spi_device_csr_aliasing | 23.280s | 1.812ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_device_mem_walk | 0.740s | 35.766us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_device_mem_partial_access | 2.330s | 59.308us | 5 | 5 | 100.00 |
| V1 | TOTAL | 65 | 115 | 56.52 | |||
| V2 | csb_read | spi_device_csb_read | 0.890s | 22.514us | 50 | 50 | 100.00 |
| V2 | mem_parity | spi_device_mem_parity | 1.110s | 119.017us | 20 | 20 | 100.00 |
| V2 | mem_cfg | spi_device_ram_cfg | 0.760s | 45.976us | 1 | 1 | 100.00 |
| V2 | tpm_read | spi_device_tpm_rw | 11.590s | 322.211us | 50 | 50 | 100.00 |
| V2 | tpm_write | spi_device_tpm_rw | 11.590s | 322.211us | 50 | 50 | 100.00 |
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 32.470s | 11.084ms | 50 | 50 | 100.00 |
| spi_device_tpm_sts_read | 1.220s | 175.617us | 50 | 50 | 100.00 | ||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 1.379m | 62.094ms | 50 | 50 | 100.00 |
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 42.700s | 168.627ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 12.350s | 5.718ms | 0 | 50 | 0.00 | ||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 35.380s | 14.912ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 12.350s | 5.718ms | 0 | 50 | 0.00 | ||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 35.380s | 14.912ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 12.350s | 5.718ms | 0 | 50 | 0.00 | ||
| V2 | cmd_info_slots | spi_device_flash_all | 12.350s | 5.718ms | 0 | 50 | 0.00 |
| V2 | cmd_read_status | spi_device_intercept | 45.390s | 19.533ms | 44 | 50 | 88.00 |
| spi_device_flash_all | 12.350s | 5.718ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_jedec | spi_device_intercept | 45.390s | 19.533ms | 44 | 50 | 88.00 |
| spi_device_flash_all | 12.350s | 5.718ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_sfdp | spi_device_intercept | 45.390s | 19.533ms | 44 | 50 | 88.00 |
| spi_device_flash_all | 12.350s | 5.718ms | 0 | 50 | 0.00 | ||
| V2 | cmd_fast_read | spi_device_intercept | 45.390s | 19.533ms | 44 | 50 | 88.00 |
| spi_device_flash_all | 12.350s | 5.718ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_pipeline | spi_device_intercept | 45.390s | 19.533ms | 44 | 50 | 88.00 |
| spi_device_flash_all | 12.350s | 5.718ms | 0 | 50 | 0.00 | ||
| V2 | flash_cmd_upload | spi_device_upload | 35.950s | 11.606ms | 35 | 50 | 70.00 |
| V2 | mailbox_command | spi_device_mailbox | 3.463m | 105.443ms | 44 | 50 | 88.00 |
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 3.463m | 105.443ms | 44 | 50 | 88.00 |
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 3.463m | 105.443ms | 44 | 50 | 88.00 |
| V2 | cmd_read_buffer | spi_device_flash_mode | 3.080m | 15.239ms | 39 | 50 | 78.00 |
| spi_device_read_buffer_direct | 19.480s | 2.770ms | 50 | 50 | 100.00 | ||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 3.463m | 105.443ms | 44 | 50 | 88.00 |
| spi_device_flash_all | 12.350s | 5.718ms | 0 | 50 | 0.00 | ||
| V2 | quad_spi | spi_device_flash_all | 12.350s | 5.718ms | 0 | 50 | 0.00 |
| V2 | dual_spi | spi_device_flash_all | 12.350s | 5.718ms | 0 | 50 | 0.00 |
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 32.160s | 3.448ms | 20 | 50 | 40.00 |
| V2 | write_enable_disable | spi_device_cfg_cmd | 32.160s | 3.448ms | 20 | 50 | 40.00 |
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 16.790s | 1.464ms | 0 | 50 | 0.00 |
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 6.890s | 545.272us | 0 | 50 | 0.00 |
| V2 | stress_all | spi_device_stress_all | 40.760s | 5.931ms | 9 | 50 | 18.00 |
| V2 | alert_test | spi_device_alert_test | 0.800s | 45.324us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_device_intr_test | 0.850s | 16.694us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 5.210s | 349.271us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_device_tl_errors | 5.210s | 349.271us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.230s | 60.865us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.890s | 125.798us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 23.280s | 1.812ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.840s | 233.090us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.230s | 60.865us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.890s | 125.798us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 23.280s | 1.812ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.840s | 233.090us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 752 | 961 | 78.25 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 1.240s | 206.161us | 5 | 5 | 100.00 |
| spi_device_tl_intg_err | 23.010s | 4.180ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 23.010s | 4.180ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 842 | 1101 | 76.48 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 22 | 22 | 14 | 63.64 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 92.14 | 97.66 | 93.02 | 98.61 | 80.85 | 96.07 | 90.90 | 87.88 |
Job spi_device_2p-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 215 failures:
0.spi_device_cfg_cmd.60320274048032781683710927744962077909688969873342534816843660023943494467639
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_cfg_cmd/latest/run.log
Job ID: smart:c43198fc-693a-4789-8445-fa8a41c8fa11
2.spi_device_cfg_cmd.33513174320879520250435406843896165781887817927620232297276709842300653052617
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_cfg_cmd/latest/run.log
Job ID: smart:39b216bd-a0be-4771-874c-47afce9c5e5a
... and 18 more failures.
0.spi_device_flash_all.109594302143552164925160857363197852897094300221899239816932857845728064481549
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_all/latest/run.log
Job ID: smart:e62071e0-cd87-4d69-a39f-98eefa70b93f
1.spi_device_flash_all.8210244763006155023349332443312094664088774004389336090682366642375602738147
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_all/latest/run.log
Job ID: smart:1cf504bb-9599-4f44-9ab2-b68001644fa2
... and 45 more failures.
0.spi_device_flash_and_tpm.3202453224279056637824525666611865183573149295054338859139205762225568197520
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:b3ad2218-2351-4968-accd-7128c7d1c2ce
1.spi_device_flash_and_tpm.70227700765893783119382472377656852508041400400379646824541304858705287406533
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:e61324cf-1fcc-4f60-88f2-e28ad04cf0d6
... and 39 more failures.
0.spi_device_flash_and_tpm_min_idle.91305736815514240931945879562589706181602861593899099529736370228061476211551
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:4874c148-6754-4e1b-a815-ce352dd62fdf
1.spi_device_flash_and_tpm_min_idle.97233966657225873373662999295039481432764812408338591825817066092452857002724
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:b7943643-a0ae-47f0-8513-3b926f68b866
... and 45 more failures.
0.spi_device_stress_all.72707428701030567682419324060505463343817851178541708054654908820754621170703
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_stress_all/latest/run.log
Job ID: smart:8e0f9d8f-d332-4adb-9be5-64ef92c4bb3b
2.spi_device_stress_all.89144552165697146540281116023398962629773092285114859153035498282776557824501
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_stress_all/latest/run.log
Job ID: smart:8a79971e-54f7-40e8-b0ab-6f3a8c281805
... and 36 more failures.
UVM_FATAL (spi_device_scoreboard.sv:726) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 23 failures:
Test spi_device_flash_all has 3 failures.
3.spi_device_flash_all.93867352154626030085988624192524397313445018974651628121251265415249298868599
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_flash_all/latest/run.log
UVM_FATAL @ 5717504587 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 5717504587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.spi_device_flash_all.105194326937222715426219899522631434487766648832534713627728487983519032371277
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_flash_all/latest/run.log
UVM_FATAL @ 1649018384 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1649018384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_device_upload has 8 failures.
9.spi_device_upload.86044718056691729981763490692534145231128738925281189674692323678989369585573
Line 259, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_upload/latest/run.log
UVM_FATAL @ 14999883779 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 14999883779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.spi_device_upload.68204375095211523715754833112321918183290274994872130340442703671850981094498
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_upload/latest/run.log
UVM_FATAL @ 606623258 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 606623258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Test spi_device_stress_all has 2 failures.
9.spi_device_stress_all.2259379049740993909010769239649493765630262635167167477803429807673481914006
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_stress_all/latest/run.log
UVM_FATAL @ 86903556 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 86903556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.spi_device_stress_all.98404333395123806256937195121063365352402018773082339224605638508682701433515
Line 257, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_stress_all/latest/run.log
UVM_FATAL @ 105335059 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 105335059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_flash_and_tpm has 8 failures.
17.spi_device_flash_and_tpm.1447214975525767426645931776646136792355970800195587715543937040666465002152
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 4301494545 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 4301494545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.spi_device_flash_and_tpm.5899375752576545021811469930796552088813111518983786817779573111371127082579
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 44750740 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 44750740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Test spi_device_flash_and_tpm_min_idle has 2 failures.
19.spi_device_flash_and_tpm_min_idle.19749690144007995667919129354550341789450103231708828399482672740904808534185
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 93424507 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 93424507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.spi_device_flash_and_tpm_min_idle.106171709411633414844689421373565358258468621570595413744163895568364516032358
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 106128481 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 106128481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 17 failures:
Test spi_device_cfg_cmd has 8 failures.
1.spi_device_cfg_cmd.68991427689241414839891455209382360542604738037172139940626562385773014110467
Line 258, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 136925385 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xaf86ca) != exp '{'{other_status:'h2be1b2, wel:'h0, busy:'h0}, '{other_status:'h2be1b2, wel:'h0, busy:'h0}}
UVM_ERROR @ 137285385 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xaf86ca) != exp '{'{other_status:'h2be1b2, wel:'h0, busy:'h0}, '{other_status:'h2be1b2, wel:'h0, busy:'h0}}
UVM_ERROR @ 137445385 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xaf86ca) != exp '{'{other_status:'h2be1b2, wel:'h0, busy:'h0}, '{other_status:'h2be1b2, wel:'h0, busy:'h0}}
UVM_ERROR @ 137625385 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xaf86ca) != exp '{'{other_status:'h2be1b2, wel:'h0, busy:'h0}, '{other_status:'h2be1b2, wel:'h0, busy:'h0}}
UVM_ERROR @ 137645385 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xaf86ca) != exp '{'{other_status:'h2be1b2, wel:'h0, busy:'h0}, '{other_status:'h2be1b2, wel:'h0, busy:'h0}}
12.spi_device_cfg_cmd.37045890699729489319858916590939644812238891646526756059643801059016201601625
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 492192186 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 493297458 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 495929058 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 496771170 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 497823810 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 1, test op = 0xb7
... and 6 more failures.
Test spi_device_upload has 7 failures.
6.spi_device_upload.112833203279586868854105186123516451585119245023328498400852855316704734556216
Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_upload/latest/run.log
UVM_ERROR @ 827456136 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 839422130 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 840055702 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 7, test op = 0x56
UVM_ERROR @ 1657262227 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 2508339313 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
14.spi_device_upload.32162364919074543391487542106793865149841434902450671712086383358100871598870
Line 259, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_upload/latest/run.log
UVM_ERROR @ 20880673424 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 21127958891 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 21136109502 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 10, test op = 0xf1
UVM_INFO @ 21156428863 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 11, test op = 0x15
UVM_INFO @ 21942157982 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 12, test op = 0x2b
... and 5 more failures.
Test spi_device_stress_all has 1 failures.
6.spi_device_stress_all.110923066073919319514663216958086581998263987513339078308972868489027500377097
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_stress_all/latest/run.log
UVM_ERROR @ 3020111467 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1d81e5) != exp '{'{other_status:'h76079, wel:'h0, busy:'h0}, '{other_status:'h76079, wel:'h0, busy:'h0}}
UVM_INFO @ 3207367690 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 1/3
UVM_INFO @ 3210342046 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/6
UVM_ERROR @ 3498572527 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1d81e6) != exp '{'{other_status:'h76079, wel:'h0, busy:'h0}, '{other_status:'h76079, wel:'h0, busy:'h0}}
UVM_ERROR @ 3502034062 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1d81e6) != exp '{'{other_status:'h76079, wel:'h0, busy:'h0}, '{other_status:'h76079, wel:'h0, busy:'h0}}
Test spi_device_flash_and_tpm_min_idle has 1 failures.
7.spi_device_flash_and_tpm_min_idle.74465127971848484964736105235894778546166170403519815065045364397484767397586
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 503766147 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x935481) != exp '{'{other_status:'h24d520, wel:'h0, busy:'h0}, '{other_status:'h24d520, wel:'h0, busy:'h0}}
UVM_FATAL @ 545271923 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 545271923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 2 failures:
24.spi_device_cfg_cmd.36256054291239947072966465218367638319203971519344100209913334445006246454609
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 291217854 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x85b08a) != exp '{'{other_status:'h2b39b2, wel:'h0, busy:'h0}, '{other_status:'h216c22, wel:'h0, busy:'h0}, '{other_status:'h216c22, wel:'h0, busy:'h0}}
UVM_ERROR @ 291606746 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x85b08a) != exp '{'{other_status:'h2b39b2, wel:'h0, busy:'h0}, '{other_status:'h216c22, wel:'h0, busy:'h0}, '{other_status:'h216c22, wel:'h0, busy:'h0}}
UVM_ERROR @ 295495666 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x85b08a) != exp '{'{other_status:'h216c22, wel:'h0, busy:'h0}, '{other_status:'h2b39b2, wel:'h0, busy:'h0}, '{other_status:'h216c22, wel:'h0, busy:'h0}, '{other_status:'h216c22, wel:'h0, busy:'h0}}
UVM_ERROR @ 331551510 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x85b08a) != exp '{'{other_status:'h216c22, wel:'h0, busy:'h0}, '{other_status:'h2b39b2, wel:'h0, busy:'h0}, '{other_status:'h216c22, wel:'h0, busy:'h0}, '{other_status:'h216c22, wel:'h0, busy:'h0}}
UVM_INFO @ 336551510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
32.spi_device_cfg_cmd.65209894902041159581855671732972901845172261179609713942859707382512704820970
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/32.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 25217116 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h119aff, wel:'h0, busy:'h0}}
UVM_INFO @ 25985514 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 1, test op = 0x4
UVM_ERROR @ 26585496 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x466bfe) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h119aff, wel:'h0, busy:'h0}, '{other_status:'h119aff, wel:'h0, busy:'h0}, '{other_status:'h19d749, wel:'h0, busy:'h0}}
UVM_ERROR @ 26848646 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x466bfe) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h119aff, wel:'h0, busy:'h0}, '{other_status:'h119aff, wel:'h0, busy:'h0}, '{other_status:'h19d749, wel:'h0, busy:'h0}}
UVM_ERROR @ 27248634 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x466bfe) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h119aff, wel:'h0, busy:'h0}, '{other_status:'h119aff, wel:'h0, busy:'h0}, '{other_status:'h19d749, wel:'h0, busy:'h0}}
UVM_ERROR (spi_device_scoreboard.sv:969) scoreboard [scoreboard] WEL mismatch: act=*, pred_fuzzy_q ('{'{other_status:*, wel:*, busy:*}} ) pred=* has 1 failures:
2.spi_device_flash_and_tpm.97362020015415553422881721491939200851523006018955183313097265255258425342096
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 502045617 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'hfc6c5, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 502132561 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'hfc6c5, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 502219505 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'hfc6c5, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 502306449 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'hfc6c5, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 502393393 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'hfc6c5, wel:'h0, busy:'h0}} ) pred=0x0
UVM_FATAL (spi_device_scoreboard.sv:1124) [scoreboard] timeout occurred! has 1 failures:
12.spi_device_flash_mode.70611514938450396336867967689723679436342290585424436860149558622082280396052
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_flash_mode/latest/run.log
UVM_FATAL @ 47619409320 ps: (spi_device_scoreboard.sv:1124) [uvm_test_top.env.scoreboard] timeout occurred!
UVM_INFO @ 47619409320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---