SPI_DEVICE/2P Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: `b938dde05c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	27.270s	5.899ms	0	50	0.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.430s	46.770us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.920s	130.781us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	36.940s	8.213ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	21.740s	1.295ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.480s	62.832us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.920s	130.781us	20	20	100.00
		spi_device_csr_aliasing	21.740s	1.295ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	39.892us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.120s	66.968us	5	5	100.00
V1		TOTAL			65	115	56.52
V2	csb_read	spi_device_csb_read	0.820s	25.045us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.160s	27.397us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.750s	18.316us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	9.860s	1.343ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.860s	1.343ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	32.810s	11.168ms	50	50	100.00
		spi_device_tpm_sts_read	1.200s	162.047us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	55.220s	33.083ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	37.410s	58.192ms	50	50	100.00
		spi_device_flash_all	4.380s	521.722us	0	50	0.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	46.580s	18.289ms	50	50	100.00
		spi_device_flash_all	4.380s	521.722us	0	50	0.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	46.580s	18.289ms	50	50	100.00
		spi_device_flash_all	4.380s	521.722us	0	50	0.00
V2	cmd_info_slots	spi_device_flash_all	4.380s	521.722us	0	50	0.00
V2	cmd_read_status	spi_device_intercept	46.690s	21.247ms	44	50	88.00
		spi_device_flash_all	4.380s	521.722us	0	50	0.00
V2	cmd_read_jedec	spi_device_intercept	46.690s	21.247ms	44	50	88.00
		spi_device_flash_all	4.380s	521.722us	0	50	0.00
V2	cmd_read_sfdp	spi_device_intercept	46.690s	21.247ms	44	50	88.00
		spi_device_flash_all	4.380s	521.722us	0	50	0.00
V2	cmd_fast_read	spi_device_intercept	46.690s	21.247ms	44	50	88.00
		spi_device_flash_all	4.380s	521.722us	0	50	0.00
V2	cmd_read_pipeline	spi_device_intercept	46.690s	21.247ms	44	50	88.00
		spi_device_flash_all	4.380s	521.722us	0	50	0.00
V2	flash_cmd_upload	spi_device_upload	58.990s	19.241ms	33	50	66.00
V2	mailbox_command	spi_device_mailbox	4.850m	44.827ms	45	50	90.00
V2	mailbox_cross_outside_command	spi_device_mailbox	4.850m	44.827ms	45	50	90.00
V2	mailbox_cross_inside_command	spi_device_mailbox	4.850m	44.827ms	45	50	90.00
V2	cmd_read_buffer	spi_device_flash_mode	2.677m	41.436ms	46	50	92.00
		spi_device_read_buffer_direct	19.870s	8.914ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	4.850m	44.827ms	45	50	90.00
		spi_device_flash_all	4.380s	521.722us	0	50	0.00
V2	quad_spi	spi_device_flash_all	4.380s	521.722us	0	50	0.00
V2	dual_spi	spi_device_flash_all	4.380s	521.722us	0	50	0.00
V2	4b_3b_feature	spi_device_cfg_cmd	41.730s	3.548ms	22	50	44.00
V2	write_enable_disable	spi_device_cfg_cmd	41.730s	3.548ms	22	50	44.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	27.270s	5.899ms	0	50	0.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	17.750s	3.046ms	0	50	0.00
V2	stress_all	spi_device_stress_all	34.510s	2.561ms	15	50	30.00
V2	alert_test	spi_device_alert_test	0.810s	19.902us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	267.294us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.090s	741.870us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.090s	741.870us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.430s	46.770us	5	5	100.00
		spi_device_csr_rw	2.920s	130.781us	20	20	100.00
		spi_device_csr_aliasing	21.740s	1.295ms	5	5	100.00
		spi_device_same_csr_outstanding	4.440s	1.242ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.430s	46.770us	5	5	100.00
		spi_device_csr_rw	2.920s	130.781us	20	20	100.00
		spi_device_csr_aliasing	21.740s	1.295ms	5	5	100.00
		spi_device_same_csr_outstanding	4.440s	1.242ms	20	20	100.00
V2		TOTAL			766	961	79.71
V2S	tl_intg_err	spi_device_sec_cm	1.180s	79.006us	5	5	100.00
		spi_device_tl_intg_err	22.770s	5.456ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.770s	5.456ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			856	1101	77.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	22	22	14	63.64
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.04	97.56	92.91	98.61	80.85	95.97	90.90	87.49

Failure Buckets

Job spi_device_2p-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 204 failures:
- Test spi_device_mailbox has 5 failures.
  - 0.spi_device_mailbox.30081257964183634750295191087793772937242952608540339947626724384054109721656
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_mailbox/latest/run.log
```
  Job ID: smart:d8752698-a2c6-4b05-b8ba-76d7ed53c938
```
  - 19.spi_device_mailbox.99578694457320076113338098883935435749389831994114653509566955776402035749291
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_mailbox/latest/run.log
```
  Job ID: smart:ce1395f6-8ebb-4d1e-8fe0-fa070c2ceac5
```
  - ... and 3 more failures.
- Test spi_device_flash_all has 45 failures.
  - 0.spi_device_flash_all.101479698748042272566904118823582479715109023111754477431360844033774824345880
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_all/latest/run.log
```
  Job ID: smart:65abac3a-4b50-480a-9507-12c927e4afc2
```
  - 1.spi_device_flash_all.44586719966001600827020854629711650780300361498429747040104464770487548928186
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_all/latest/run.log
```
  Job ID: smart:df867d5c-6526-4f54-915f-066111d8d4db
```
  - ... and 43 more failures.
- Test spi_device_flash_and_tpm has 43 failures.
  - 0.spi_device_flash_and_tpm.62532059547885509331376396264635242851119918402023875375904447547083289277286
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log
```
  Job ID: smart:e201688d-d8b7-4813-9b30-9693cb64ce08
```
  - 1.spi_device_flash_and_tpm.68853739177410248334982833079549809289083800506617464482638179294253050341677
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log
```
  Job ID: smart:492443b4-9f29-41bc-984a-9ec69b4dae8d
```
  - ... and 41 more failures.
- Test spi_device_flash_and_tpm_min_idle has 45 failures.
  - 0.spi_device_flash_and_tpm_min_idle.99381032668745385912295542062515432934911612237594343568717361495999222939234
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  Job ID: smart:0825fa53-a453-482f-b15a-e047f667ee56
```
  - 1.spi_device_flash_and_tpm_min_idle.24932487218742179633657351506076854041378805900964288754546708647207775332534
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  Job ID: smart:68c624a6-5968-4e47-9ccc-0c9d3f169fa5
```
  - ... and 43 more failures.
- Test spi_device_cfg_cmd has 23 failures.
  - 2.spi_device_cfg_cmd.17455588693231692387884427830549328886185218985716503301598502258087971579888
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_cfg_cmd/latest/run.log
```
  Job ID: smart:8d98808e-01d0-4116-8be8-63a03ced3a10
```
  - 3.spi_device_cfg_cmd.81042652686343881720124355238481858484876446533623385234788347720194115265692
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_cfg_cmd/latest/run.log
```
  Job ID: smart:9ad0172a-6a73-4ade-bc52-03997fc8de96
```
  - ... and 21 more failures.
- ... and 3 more tests.

UVM_FATAL (spi_device_scoreboard.sv:726) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 24 failures:

Test spi_device_upload has 11 failures.

0.spi_device_upload.78334473336262617276398741468766258770918235935961592429024289962687220922688
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_upload/latest/run.log

  UVM_FATAL @ 630267661 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 630267661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.spi_device_upload.29616209183607087266622516442694481577975087217311072206843416086982814311919
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_upload/latest/run.log

  UVM_FATAL @ 878113778 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 878113778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

Test spi_device_flash_all has 5 failures.

2.spi_device_flash_all.106588843493043100660103824609102526226364012557318125308176546785289231999594
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_flash_all/latest/run.log

  UVM_FATAL @ 610338868 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 610338868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.spi_device_flash_all.34587637624352899163686617803655348875369799643375962442304634955529672157923
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_flash_all/latest/run.log

  UVM_FATAL @ 126519422 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 126519422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test spi_device_flash_and_tpm_min_idle has 3 failures.

4.spi_device_flash_and_tpm_min_idle.9051308717139511485621260459085942871778831630244803999034098608576315754228
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_FATAL @ 191031369 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 191031369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.spi_device_flash_and_tpm_min_idle.58071907287836953512462233899717520211293187873705026320723864233696492627540
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_FATAL @ 3045694963 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 3045694963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test spi_device_flash_and_tpm has 4 failures.

16.spi_device_flash_and_tpm.96717621172499391453022483386021021863523513494310498178513003126123821534982
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/16.spi_device_flash_and_tpm/latest/run.log

  UVM_FATAL @ 7821724272 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 7821724272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.spi_device_flash_and_tpm.95679440872048951319638680415497251511795773450065067733731985603566706319227
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/35.spi_device_flash_and_tpm/latest/run.log

  UVM_FATAL @  90636629 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  90636629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test spi_device_stress_all has 1 failures.

44.spi_device_stress_all.102106760468020991255914017093068087105223407232917796474437927247670577395995
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/44.spi_device_stress_all/latest/run.log

  UVM_FATAL @ 4132811179 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 4132811179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 12 failures:

Test spi_device_upload has 6 failures.

1.spi_device_upload.66198094177235753155954209102911343803101005558227726169354538316488777867118
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_upload/latest/run.log

  UVM_ERROR @  21585384 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @  33075384 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_INFO @  35401384 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 1, test op = 0x5
  UVM_INFO @ 282695384 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 2, test op = 0x51
  UVM_INFO @ 532527384 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 3, test op = 0x5b

6.spi_device_upload.61854279820285575890651175283432896794087063663667066251248540328487186608319
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_upload/latest/run.log

  UVM_ERROR @ 2979303434 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 3411928434 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_INFO @ 3416235434 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 4, test op = 0x5a
  UVM_INFO @ 10302161684 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 5, test op = 0xb
  UVM_INFO @ 10704584184 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 6, test op = 0x98

... and 4 more failures.

Test spi_device_flash_and_tpm has 2 failures.

4.spi_device_flash_and_tpm.33554239012993516638022699975137178081761528618993974636116565164389892380611
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 438264362 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_FATAL @ 446754842 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 446754842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.spi_device_flash_and_tpm.106135010146018663543054817344665502368762968949539785673426980761897680065388
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 563252330 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_FATAL @ 567944331 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 567944331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_flash_and_tpm_min_idle has 2 failures.

9.spi_device_flash_and_tpm_min_idle.83628752521992726032314894467256228750560446223513903615786703231673489309390
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @  55911937 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_FATAL @  56065984 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  56065984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.spi_device_flash_and_tpm_min_idle.94032675213084490511839777028362356617597670052180090215883527709886972599790
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 2751484128 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_FATAL @ 2960913889 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 2960913889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_cfg_cmd has 2 failures.

23.spi_device_cfg_cmd.28641060655548576898960035262872131777957918983417687661157588376420502699812
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @  40493279 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @  42323101 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_INFO @  42578425 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 1, test op = 0x4
  UVM_ERROR @  42727364 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @  42918857 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}

34.spi_device_cfg_cmd.99672297839245142150855553912874049513333171734661243178450124136437597646196
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/34.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 2756890127 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x6fa7be) != exp '{'{other_status:'h1be9ef, wel:'h0, busy:'h0}, '{other_status:'h1be9ef, wel:'h0, busy:'h0}}
  UVM_INFO @ 2763942815 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 6, test op = 0x4
  UVM_ERROR @ 2765205983 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x83bc8e) != exp '{'{other_status:'h1be9ef, wel:'h0, busy:'h0}, '{other_status:'h20ef23, wel:'h0, busy:'h0}, '{other_status:'h20ef23, wel:'h0, busy:'h0}}
  UVM_INFO @ 2775469223 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 7, test op = 0x4
  UVM_INFO @ 2786627207 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 8, test op = 0x4

Test spi_device_cfg_cmd has 3 failures.

1.spi_device_cfg_cmd.44095568046093244322131289263733054495987208409916321584454417475186692229241
Line 259, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 2829119238 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xa62582) != exp '{'{other_status:'h298960, wel:'h0, busy:'h0}, '{other_status:'h310265, wel:'h0, busy:'h0}, '{other_status:'h310265, wel:'h0, busy:'h0}}
  UVM_ERROR @ 2829239238 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xa62582) != exp '{'{other_status:'h298960, wel:'h0, busy:'h0}, '{other_status:'h310265, wel:'h0, busy:'h0}, '{other_status:'h310265, wel:'h0, busy:'h0}}
  UVM_ERROR @ 2829439238 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xa62582) != exp '{'{other_status:'h298960, wel:'h0, busy:'h0}, '{other_status:'h310265, wel:'h0, busy:'h0}, '{other_status:'h310265, wel:'h0, busy:'h0}}
  UVM_ERROR @ 2829559238 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xa62582) != exp '{'{other_status:'h298960, wel:'h0, busy:'h0}, '{other_status:'h310265, wel:'h0, busy:'h0}, '{other_status:'h310265, wel:'h0, busy:'h0}}
  UVM_ERROR @ 2829689238 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xa62582) != exp '{'{other_status:'h298960, wel:'h0, busy:'h0}, '{other_status:'h310265, wel:'h0, busy:'h0}, '{other_status:'h310265, wel:'h0, busy:'h0}}

43.spi_device_cfg_cmd.40955180315324472456774242878013705917387303624141837429992808708374953594334
Line 258, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 669089700 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1573e) != exp '{'{other_status:'h55cf, wel:'h0, busy:'h0}, '{other_status:'h55cf, wel:'h0, busy:'h0}, '{other_status:'h1b0ab2, wel:'h0, busy:'h0}}
  UVM_ERROR @ 669464700 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1573e) != exp '{'{other_status:'h55cf, wel:'h0, busy:'h0}, '{other_status:'h55cf, wel:'h0, busy:'h0}, '{other_status:'h1b0ab2, wel:'h0, busy:'h0}}
  UVM_ERROR @ 672933450 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1573e) != exp '{'{other_status:'h55cf, wel:'h0, busy:'h0}, '{other_status:'h1b0ab2, wel:'h0, busy:'h0}, '{other_status:'h55cf, wel:'h0, busy:'h0}, '{other_status:'h797b, wel:'h0, busy:'h0}}
  UVM_ERROR @ 673339700 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1573e) != exp '{'{other_status:'h55cf, wel:'h0, busy:'h0}, '{other_status:'h1b0ab2, wel:'h0, busy:'h0}, '{other_status:'h55cf, wel:'h0, busy:'h0}, '{other_status:'h797b, wel:'h0, busy:'h0}}
  UVM_ERROR @ 673402200 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1573e) != exp '{'{other_status:'h55cf, wel:'h0, busy:'h0}, '{other_status:'h1b0ab2, wel:'h0, busy:'h0}, '{other_status:'h55cf, wel:'h0, busy:'h0}, '{other_status:'h797b, wel:'h0, busy:'h0}}

... and 1 more failures.

Test spi_device_flash_and_tpm has 1 failures.

5.spi_device_flash_and_tpm.106575599784260252242062131086595636093853736128881955773417022882601913742529
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 511124353 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc4400e) != exp '{'{other_status:'h311003, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h311003, wel:'h0, busy:'h0}, '{other_status:'h311003, wel:'h0, busy:'h0}}
  UVM_ERROR @ 1267338736 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc4400e) != exp '{'{other_status:'h311003, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h311003, wel:'h0, busy:'h0}, '{other_status:'h311003, wel:'h0, busy:'h0}}
  UVM_ERROR @ 1291547263 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc4400e) != exp '{'{other_status:'h311003, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h311003, wel:'h0, busy:'h0}, '{other_status:'h311003, wel:'h0, busy:'h0}}
  UVM_ERROR @ 1336964293 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc4400e) != exp '{'{other_status:'h311003, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h311003, wel:'h0, busy:'h0}, '{other_status:'h311003, wel:'h0, busy:'h0}}
  UVM_ERROR @ 1443846134 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0

Test spi_device_stress_all has 1 failures.

46.spi_device_stress_all.20344608779545873740736777204847431422357490731579245059327226620287849415005
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/46.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 351663838 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xad231e) != exp '{'{other_status:'h2b48c7, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h2b48c7, wel:'h0, busy:'h0}, '{other_status:'h2b48c7, wel:'h0, busy:'h0}}
  UVM_ERROR @ 462340495 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xad231e) != exp '{'{other_status:'h2b48c7, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h2b48c7, wel:'h0, busy:'h0}, '{other_status:'h2b48c7, wel:'h0, busy:'h0}}
  UVM_ERROR @ 464421301 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xad231e) != exp '{'{other_status:'h2b48c7, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h2b48c7, wel:'h0, busy:'h0}, '{other_status:'h2b48c7, wel:'h0, busy:'h0}}
  UVM_ERROR @ 465986956 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xad231e) != exp '{'{other_status:'h2b48c7, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h2b48c7, wel:'h0, busy:'h0}, '{other_status:'h2b48c7, wel:'h0, busy:'h0}}
  UVM_ERROR @ 471128365 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xad231e) != exp '{'{other_status:'h2b48c7, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h2b48c7, wel:'h0, busy:'h0}, '{other_status:'h2b48c7, wel:'h0, busy:'h0}}