SPI_DEVICE/2P Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: `ae68723071`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	54.670s	25.150ms	0	50	0.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.450s	44.335us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.910s	106.827us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	39.550s	10.856ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	21.360s	306.182us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.090s	140.785us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.910s	106.827us	20	20	100.00
		spi_device_csr_aliasing	21.360s	306.182us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.710s	10.429us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.160s	213.622us	5	5	100.00
V1		TOTAL			65	115	56.52
V2	csb_read	spi_device_csb_read	0.830s	21.572us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.100s	91.319us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	36.380us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	15.720s	1.583ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	15.720s	1.583ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	35.090s	11.595ms	50	50	100.00
		spi_device_tpm_sts_read	1.170s	162.419us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.401m	17.354ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	28.800s	118.965ms	50	50	100.00
		spi_device_flash_all	14.760s	1.605ms	0	50	0.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	58.280s	46.629ms	50	50	100.00
		spi_device_flash_all	14.760s	1.605ms	0	50	0.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	58.280s	46.629ms	50	50	100.00
		spi_device_flash_all	14.760s	1.605ms	0	50	0.00
V2	cmd_info_slots	spi_device_flash_all	14.760s	1.605ms	0	50	0.00
V2	cmd_read_status	spi_device_intercept	41.610s	4.146ms	43	50	86.00
		spi_device_flash_all	14.760s	1.605ms	0	50	0.00
V2	cmd_read_jedec	spi_device_intercept	41.610s	4.146ms	43	50	86.00
		spi_device_flash_all	14.760s	1.605ms	0	50	0.00
V2	cmd_read_sfdp	spi_device_intercept	41.610s	4.146ms	43	50	86.00
		spi_device_flash_all	14.760s	1.605ms	0	50	0.00
V2	cmd_fast_read	spi_device_intercept	41.610s	4.146ms	43	50	86.00
		spi_device_flash_all	14.760s	1.605ms	0	50	0.00
V2	cmd_read_pipeline	spi_device_intercept	41.610s	4.146ms	43	50	86.00
		spi_device_flash_all	14.760s	1.605ms	0	50	0.00
V2	flash_cmd_upload	spi_device_upload	32.720s	14.252ms	37	50	74.00
V2	mailbox_command	spi_device_mailbox	2.483m	29.872ms	46	50	92.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.483m	29.872ms	46	50	92.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.483m	29.872ms	46	50	92.00
V2	cmd_read_buffer	spi_device_flash_mode	2.594m	11.780ms	48	50	96.00
		spi_device_read_buffer_direct	16.720s	3.010ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.483m	29.872ms	46	50	92.00
		spi_device_flash_all	14.760s	1.605ms	0	50	0.00
V2	quad_spi	spi_device_flash_all	14.760s	1.605ms	0	50	0.00
V2	dual_spi	spi_device_flash_all	14.760s	1.605ms	0	50	0.00
V2	4b_3b_feature	spi_device_cfg_cmd	23.130s	5.502ms	17	50	34.00
V2	write_enable_disable	spi_device_cfg_cmd	23.130s	5.502ms	17	50	34.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	54.670s	25.150ms	0	50	0.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	19.950s	8.366ms	1	50	2.00
V2	stress_all	spi_device_stress_all	1.347m	21.027ms	11	50	22.00
V2	alert_test	spi_device_alert_test	0.800s	15.731us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.790s	17.525us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.580s	243.287us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.580s	243.287us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.450s	44.335us	5	5	100.00
		spi_device_csr_rw	2.910s	106.827us	20	20	100.00
		spi_device_csr_aliasing	21.360s	306.182us	5	5	100.00
		spi_device_same_csr_outstanding	4.440s	408.870us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.450s	44.335us	5	5	100.00
		spi_device_csr_rw	2.910s	106.827us	20	20	100.00
		spi_device_csr_aliasing	21.360s	306.182us	5	5	100.00
		spi_device_same_csr_outstanding	4.440s	408.870us	20	20	100.00
V2		TOTAL			764	961	79.50
V2S	tl_intg_err	spi_device_sec_cm	1.280s	143.488us	5	5	100.00
		spi_device_tl_intg_err	22.270s	3.766ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.270s	3.766ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			854	1101	77.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	22	22	14	63.64
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.19	97.58	92.94	98.61	80.85	96.00	90.90	88.43

Failure Buckets

Job spi_device_2p-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 208 failures:
- Test spi_device_flash_all has 42 failures.
  - 0.spi_device_flash_all.46713643187136222592359798393485276185934304454407645577201557597534374399164
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_all/latest/run.log
```
  Job ID: smart:f461096a-e538-428d-ad07-5cad0d4a03dd
```
  - 1.spi_device_flash_all.11709716540183264858777375413978556576386393801504362104797215714086822826711
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_all/latest/run.log
```
  Job ID: smart:8e7346a9-8615-4c2b-a3f8-44902b040b57
```
  - ... and 40 more failures.
- Test spi_device_flash_and_tpm has 46 failures.
  - 0.spi_device_flash_and_tpm.43934325334740670459294059441565703745868116916085892109090725956830222061919
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log
```
  Job ID: smart:786e2cd4-5ed0-4220-bdb5-594fec6921d9
```
  - 1.spi_device_flash_and_tpm.62374035554485154178933049929456136436933425580755987827650111121331696702919
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log
```
  Job ID: smart:697415ad-0f13-4baa-9b9e-0b80832a327f
```
  - ... and 44 more failures.
- Test spi_device_flash_and_tpm_min_idle has 46 failures.
  - 0.spi_device_flash_and_tpm_min_idle.76881746307782447507249973440571361604131563626846786290852209163754059158505
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  Job ID: smart:c2e5b74f-16d3-47be-b455-1f2eda7fae12
```
  - 1.spi_device_flash_and_tpm_min_idle.29018848144569987541269374689481494425321644077493683967739806952425883283352
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  Job ID: smart:32a92800-703b-4594-a693-24db834d08bd
```
  - ... and 44 more failures.
- Test spi_device_stress_all has 37 failures.
  - 0.spi_device_stress_all.49447227049314265972511985201442575285624759456758182401204693850414853890873
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_stress_all/latest/run.log
```
  Job ID: smart:9ba223b4-8006-494c-8d0f-31537ccd2672
```
  - 1.spi_device_stress_all.72005837500762465138471138674698183374777489883204450313773116484862745491376
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_stress_all/latest/run.log
```
  Job ID: smart:e434ced2-0602-4c5d-895a-8120ce4d84ba
```
  - ... and 35 more failures.
- Test spi_device_mailbox has 4 failures.
  - 1.spi_device_mailbox.53901083749905258835820353193602643019372119423624066999855184739229231167904
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_mailbox/latest/run.log
```
  Job ID: smart:64b4e33a-d3fa-4f5f-94c4-28c3d89239a7
```
  - 3.spi_device_mailbox.101879456003072959046452384227668085725506736315424526198496396220096302266531
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_mailbox/latest/run.log
```
  Job ID: smart:6d95c6b6-720d-491a-89ba-9c4a94122940
```
  - ... and 2 more failures.
- ... and 3 more tests.

UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 20 failures:

Test spi_device_cfg_cmd has 7 failures.

0.spi_device_cfg_cmd.109456402483939556623282447177226000007659096119802938989207596963172080275463
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 249674452 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xa3c9e6) != exp '{'{other_status:'h28f279, wel:'h0, busy:'h0}, '{other_status:'h28f279, wel:'h0, busy:'h0}}
  UVM_ERROR @ 249846169 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xa3c9e6) != exp '{'{other_status:'h28f279, wel:'h0, busy:'h0}, '{other_status:'h28f279, wel:'h0, busy:'h0}}
  UVM_ERROR @ 250098694 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xa3c9e6) != exp '{'{other_status:'h28f279, wel:'h0, busy:'h0}, '{other_status:'h28f279, wel:'h0, busy:'h0}}
  UVM_INFO @ 250260310 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 5, test op = 0xe9
  UVM_ERROR @ 250371421 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xa3c9e6) != exp '{'{other_status:'h28f279, wel:'h0, busy:'h0}, '{other_status:'h28f279, wel:'h0, busy:'h0}}

9.spi_device_cfg_cmd.98488978936420773023145450171382725952617172512938368147704357151529331210356
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 107461601 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x3b4c46) != exp '{'{other_status:'hed311, wel:'h0, busy:'h0}, '{other_status:'hed311, wel:'h0, busy:'h0}}
  UVM_ERROR @ 108461609 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x3b4c46) != exp '{'{other_status:'hed311, wel:'h0, busy:'h0}, '{other_status:'hed311, wel:'h0, busy:'h0}}
  UVM_ERROR @ 109378283 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x3b4c46) != exp '{'{other_status:'hed311, wel:'h0, busy:'h0}, '{other_status:'hed311, wel:'h0, busy:'h0}}
  UVM_ERROR @ 109878287 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x3b4c46) != exp '{'{other_status:'hed311, wel:'h0, busy:'h0}, '{other_status:'hed311, wel:'h0, busy:'h0}}
  UVM_INFO @ 111294965 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 3, test op = 0x4

... and 5 more failures.

Test spi_device_upload has 10 failures.

5.spi_device_upload.5739746487611404122991879789772287856790763771769427489717081653895886168889
Line 257, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_upload/latest/run.log

  UVM_ERROR @ 14841917139 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 14852517139 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_INFO @ 14860010139 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 8, test op = 0xf4
  UVM_ERROR @ 15014717139 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 15043077139 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}

9.spi_device_upload.48518336872212691921729733265236327549243461385795645739127702283759462969235
Line 261, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_upload/latest/run.log

  UVM_ERROR @ 322317088 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 350463822 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_INFO @ 350919288 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 12, test op = 0xba
  UVM_INFO @ 435435131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test spi_device_stress_all has 2 failures.

18.spi_device_stress_all.105144917454110690027574733064464148291271141952104701163817917986374750973433
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 2926348101 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x6f2f86) != exp '{'{other_status:'h1bcbe1, wel:'h0, busy:'h0}, '{other_status:'h1bcbe1, wel:'h0, busy:'h0}}
  UVM_INFO @ 14352968101 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/6
  UVM_INFO @ 15896028101 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/6
  UVM_INFO @ 17440668101 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 4/6
  UVM_INFO @ 18732668101 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 5/6

47.spi_device_stress_all.29447099034738085751195694898215817996785698816879237727469141970074063204433
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 962536568 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x9933f9) != exp '{'{other_status:'h264cfe, wel:'h0, busy:'h0}, '{other_status:'h264cfe, wel:'h0, busy:'h0}}
  UVM_FATAL @ 966863994 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 966863994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_flash_and_tpm has 1 failures.

44.spi_device_flash_and_tpm.31782551099821195298215241908351510508688377075975433896821677776447871706538
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/44.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 25079686874 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x13b189) != exp '{'{other_status:'h4ec62, wel:'h0, busy:'h0}, '{other_status:'h4ec62, wel:'h0, busy:'h0}}
  UVM_FATAL @ 25150334116 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 25150334116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (spi_device_scoreboard.sv:726) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 15 failures:

Test spi_device_flash_and_tpm has 3 failures.

3.spi_device_flash_and_tpm.16542553542007748975416021411591286199376949160105663517684320756482541129474
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_flash_and_tpm/latest/run.log

  UVM_FATAL @ 1226227017 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1226227017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.spi_device_flash_and_tpm.59719548370022900203322971074666769856300548806197484154875074402634482449629
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_flash_and_tpm/latest/run.log

  UVM_FATAL @ 1118973837 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1118973837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test spi_device_flash_all has 7 failures.

6.spi_device_flash_all.74469124039956241898452329961013485963470873158930372028519701206446671128273
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_flash_all/latest/run.log

  UVM_FATAL @ 5917285808 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 5917285808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.spi_device_flash_all.38700385423069150795450101239950921712966760757305863170406459240657696712464
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_flash_all/latest/run.log

  UVM_FATAL @ 2038170777 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 2038170777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test spi_device_upload has 3 failures.

15.spi_device_upload.54702309743192391558317728916384935833319730587470495453812797392487397747077
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_upload/latest/run.log

  UVM_FATAL @  66813092 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  66813092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.spi_device_upload.25134645802172814081517831122586525593235661590020571913008264010529429388601
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/19.spi_device_upload/latest/run.log

  UVM_FATAL @ 6918388796 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 6918388796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test spi_device_flash_and_tpm_min_idle has 2 failures.

15.spi_device_flash_and_tpm_min_idle.23889891986284973461673040378273606224555418687656213916230627294024122726881
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_FATAL @ 144869361 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 144869361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

29.spi_device_flash_and_tpm_min_idle.93668260260761044382137059086998290147763661983954792433849575193838113300686
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_FATAL @ 1346605719 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1346605719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_cfg_cmd has 2 failures.

42.spi_device_cfg_cmd.6301353192285382982418675719970128774402757382972696766304089245157158592983
Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/42.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 221803075 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x83c4e6) != exp '{'{other_status:'h20f139, wel:'h0, busy:'h0}, '{other_status:'h1ba287, wel:'h0, busy:'h0}, '{other_status:'h1ba287, wel:'h0, busy:'h0}}
  UVM_ERROR @ 221863075 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x6e8a1e) != exp '{'{other_status:'h20f139, wel:'h0, busy:'h0}, '{other_status:'h1ba287, wel:'h0, busy:'h0}, '{other_status:'h1ba287, wel:'h0, busy:'h0}}
  UVM_INFO @ 222073075 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 7, test op = 0xb7
  UVM_ERROR @ 222303075 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x6e8a1e) != exp '{'{other_status:'h20f139, wel:'h0, busy:'h0}, '{other_status:'h1ba287, wel:'h0, busy:'h0}, '{other_status:'h1ba287, wel:'h0, busy:'h0}}
  UVM_ERROR @ 222513075 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x6e8a1e) != exp '{'{other_status:'h20f139, wel:'h0, busy:'h0}, '{other_status:'h1ba287, wel:'h0, busy:'h0}, '{other_status:'h1ba287, wel:'h0, busy:'h0}, '{other_status:'h1d9ce6, wel:'h0, busy:'h0}}

47.spi_device_cfg_cmd.106445446533780477450047790566857637887112905985780705888557775617824654863725
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @  19256670 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h1bf4c1, wel:'h0, busy:'h0}}
  UVM_ERROR @  19386670 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h1bf4c1, wel:'h0, busy:'h0}}
  UVM_ERROR @  19496670 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h1bf4c1, wel:'h0, busy:'h0}}
  UVM_ERROR @  19776670 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h1bf4c1, wel:'h0, busy:'h0}}
  UVM_ERROR @  19916670 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h1bf4c1, wel:'h0, busy:'h0}}

UVM_ERROR (spi_device_scoreboard.sv:969) scoreboard [scoreboard] WEL mismatch: act=*, pred_fuzzy_q ('{}) pred=* has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

2.spi_device_flash_and_tpm_min_idle.75756005253578367003210131076023182666617158270958439122511796807967297533277
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 1208965820 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
  UVM_ERROR @ 1209147628 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
  UVM_ERROR @ 1209329436 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
  UVM_ERROR @ 1209511244 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
  UVM_ERROR @ 1209693052 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0

Test spi_device_flash_all has 1 failures.

13.spi_device_flash_all.96100336513103045622193557117621521432113190700712699985430335422438182456127
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 5096450317 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x22d0a6) != exp '{'{other_status:'h8b429, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h8b429, wel:'h0, busy:'h0}, '{other_status:'h8b429, wel:'h0, busy:'h0}}
  UVM_FATAL @ 5110810318 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 5110810318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---