0cb61fc7e7| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_flash_and_tpm | 1.128m | 16.120ms | 1 | 50 | 2.00 |
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.460s | 49.789us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_device_csr_rw | 2.750s | 111.364us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 33.460s | 1.069ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_device_csr_aliasing | 20.670s | 1.260ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 3.870s | 162.873us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 2.750s | 111.364us | 20 | 20 | 100.00 |
| spi_device_csr_aliasing | 20.670s | 1.260ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_device_mem_walk | 0.690s | 34.218us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_device_mem_partial_access | 2.180s | 63.444us | 5 | 5 | 100.00 |
| V1 | TOTAL | 66 | 115 | 57.39 | |||
| V2 | csb_read | spi_device_csb_read | 0.860s | 20.813us | 50 | 50 | 100.00 |
| V2 | mem_parity | spi_device_mem_parity | 1.090s | 64.101us | 20 | 20 | 100.00 |
| V2 | mem_cfg | spi_device_ram_cfg | 0.750s | 32.335us | 1 | 1 | 100.00 |
| V2 | tpm_read | spi_device_tpm_rw | 9.900s | 927.417us | 50 | 50 | 100.00 |
| V2 | tpm_write | spi_device_tpm_rw | 9.900s | 927.417us | 50 | 50 | 100.00 |
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 30.910s | 10.589ms | 50 | 50 | 100.00 |
| spi_device_tpm_sts_read | 1.110s | 139.016us | 50 | 50 | 100.00 | ||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 1.091m | 13.291ms | 50 | 50 | 100.00 |
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 44.100s | 20.139ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 17.560s | 9.007ms | 0 | 50 | 0.00 | ||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 28.650s | 40.131ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 17.560s | 9.007ms | 0 | 50 | 0.00 | ||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 28.650s | 40.131ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 17.560s | 9.007ms | 0 | 50 | 0.00 | ||
| V2 | cmd_info_slots | spi_device_flash_all | 17.560s | 9.007ms | 0 | 50 | 0.00 |
| V2 | cmd_read_status | spi_device_intercept | 32.550s | 3.315ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 17.560s | 9.007ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_jedec | spi_device_intercept | 32.550s | 3.315ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 17.560s | 9.007ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_sfdp | spi_device_intercept | 32.550s | 3.315ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 17.560s | 9.007ms | 0 | 50 | 0.00 | ||
| V2 | cmd_fast_read | spi_device_intercept | 32.550s | 3.315ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 17.560s | 9.007ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_pipeline | spi_device_intercept | 32.550s | 3.315ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 17.560s | 9.007ms | 0 | 50 | 0.00 | ||
| V2 | flash_cmd_upload | spi_device_upload | 37.310s | 46.105ms | 36 | 50 | 72.00 |
| V2 | mailbox_command | spi_device_mailbox | 2.779m | 40.086ms | 46 | 50 | 92.00 |
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 2.779m | 40.086ms | 46 | 50 | 92.00 |
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 2.779m | 40.086ms | 46 | 50 | 92.00 |
| V2 | cmd_read_buffer | spi_device_flash_mode | 2.543m | 10.551ms | 39 | 50 | 78.00 |
| spi_device_read_buffer_direct | 22.840s | 7.038ms | 50 | 50 | 100.00 | ||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 2.779m | 40.086ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 17.560s | 9.007ms | 0 | 50 | 0.00 | ||
| V2 | quad_spi | spi_device_flash_all | 17.560s | 9.007ms | 0 | 50 | 0.00 |
| V2 | dual_spi | spi_device_flash_all | 17.560s | 9.007ms | 0 | 50 | 0.00 |
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 40.700s | 11.209ms | 25 | 50 | 50.00 |
| V2 | write_enable_disable | spi_device_cfg_cmd | 40.700s | 11.209ms | 25 | 50 | 50.00 |
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 1.128m | 16.120ms | 1 | 50 | 2.00 |
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 43.990s | 5.057ms | 0 | 50 | 0.00 |
| V2 | stress_all | spi_device_stress_all | 22.380s | 5.057ms | 11 | 50 | 22.00 |
| V2 | alert_test | spi_device_alert_test | 0.760s | 13.843us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_device_intr_test | 0.800s | 21.177us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 5.200s | 210.034us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_device_tl_errors | 5.200s | 210.034us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.460s | 49.789us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.750s | 111.364us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 20.670s | 1.260ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.770s | 166.136us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.460s | 49.789us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.750s | 111.364us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 20.670s | 1.260ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.770s | 166.136us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 764 | 961 | 79.50 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 1.230s | 232.490us | 5 | 5 | 100.00 |
| spi_device_tl_intg_err | 22.420s | 993.861us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 22.420s | 993.861us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 855 | 1101 | 77.66 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 22 | 22 | 14 | 63.64 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 92.21 | 97.67 | 93.04 | 98.61 | 80.85 | 96.09 | 90.90 | 88.33 |
Job spi_device_2p-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 207 failures:
0.spi_device_intercept.86380540294661938355510860155890092649040324640818104783205691729299093103020
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_intercept/latest/run.log
Job ID: smart:588689be-452d-4044-9862-5bb87420d8e8
7.spi_device_intercept.94020699723094044235419409414402753678537362009318565416029675149992366612387
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_intercept/latest/run.log
Job ID: smart:597b68bc-8de3-4702-b1e9-0175f65def27
... and 2 more failures.
0.spi_device_cfg_cmd.86688755479071821664546667536637260366489120933392386823584997306452253089096
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_cfg_cmd/latest/run.log
Job ID: smart:a6c7071d-e5dc-4c0d-81d3-e65c5c8ad7eb
3.spi_device_cfg_cmd.11417732470676745219031552165250959687230679125830833388019076544607985441791
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_cfg_cmd/latest/run.log
Job ID: smart:0ce80ee4-d192-4d73-ba40-76f1a5b444fe
... and 20 more failures.
0.spi_device_flash_all.93652239731464264739121421839048041938685822584383530653201541541921490156177
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_all/latest/run.log
Job ID: smart:88be5ea2-54b0-4cf8-9a72-a37699246b3a
1.spi_device_flash_all.111801244469961065917383314945421845961215532279398563022817546571609454506100
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_all/latest/run.log
Job ID: smart:fdfb9d90-56b8-48a9-b8da-a0428a2dcb27
... and 41 more failures.
0.spi_device_flash_and_tpm.83045753054063088717787917127464869743381823353988981553436395761685442627148
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:d4f1961d-8733-4c5a-8d1e-c961e33f025b
1.spi_device_flash_and_tpm.82812030712309827277482068020777480800773804109111698029488499777052457822206
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:af0f0568-a2de-4936-9bb2-2643d3c23011
... and 41 more failures.
0.spi_device_flash_and_tpm_min_idle.66340301970707825045385489284671704030281793235350592323160119457553117005928
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:3460abcc-acb7-44f8-a4cf-148eca0c7ca0
1.spi_device_flash_and_tpm_min_idle.110298776776508811570037894304451698277666669490617465324388297032009352700988
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:afcba8c5-f4ec-4f7d-b292-7fc4e7041e2a
... and 44 more failures.
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 19 failures:
Test spi_device_upload has 8 failures.
0.spi_device_upload.111825255304880748032486398856447697571670261154287144437172517569671302642100
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_upload/latest/run.log
UVM_ERROR @ 1366235901 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 1685251630 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 1687536262 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 2, test op = 0xb
UVM_INFO @ 6137367398 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 3, test op = 0x1f
UVM_INFO @ 6675838526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
11.spi_device_upload.23025764668163151013420118569717939584715148545426375428627835867773611844066
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_upload/latest/run.log
UVM_ERROR @ 968237906 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 1008874676 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 1013251882 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 5, test op = 0x72
UVM_INFO @ 1165907689 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 6, test op = 0x35
UVM_INFO @ 1562033210 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 7, test op = 0x35
... and 6 more failures.
Test spi_device_stress_all has 2 failures.
3.spi_device_stress_all.111563818659310329246878539823559600660644271663786123044320974179738484155978
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_stress_all/latest/run.log
UVM_ERROR @ 7562281847 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 7703051848 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 7703051848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.spi_device_stress_all.34793082440804191194637420164511881740694307714342811294213826184872365968588
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_stress_all/latest/run.log
UVM_ERROR @ 80716058 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 100867648 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 100867648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_flash_and_tpm has 1 failures.
8.spi_device_flash_and_tpm.75736147618399613799007183241389799757303085784152047097891996103503716105033
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 5877178328 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 5970326054 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 5970326054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_cfg_cmd has 2 failures.
11.spi_device_cfg_cmd.86496930828102499769996061321278192220930503139912631734602719675952926430427
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 132717029 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xee615a) != exp '{'{other_status:'h3b9856, wel:'h0, busy:'h0}, '{other_status:'h3b9856, wel:'h0, busy:'h0}}
UVM_ERROR @ 132747641 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xee615a) != exp '{'{other_status:'h3b9856, wel:'h0, busy:'h0}, '{other_status:'h3b9856, wel:'h0, busy:'h0}}
UVM_ERROR @ 133329269 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xee615a) != exp '{'{other_status:'h3b9856, wel:'h0, busy:'h0}, '{other_status:'h3b9856, wel:'h0, busy:'h0}}
UVM_ERROR @ 133696613 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xee615a) != exp '{'{other_status:'h3b9856, wel:'h0, busy:'h0}, '{other_status:'h3b9856, wel:'h0, busy:'h0}}
UVM_INFO @ 134084365 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 5, test op = 0x6
25.spi_device_cfg_cmd.48879005672135065056817240336651641794164740173858318782963840740218200463715
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/25.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 24987598 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 25752898 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 25885550 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 26099834 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 26365138 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 1, test op = 0xe9
Test spi_device_flash_all has 2 failures.
12.spi_device_flash_all.76248867184275584159726352427471560847117380220190274156451115864910088825220
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_flash_all/latest/run.log
UVM_ERROR @ 1971127732 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xa10d99) != exp '{'{other_status:'h284366, wel:'h0, busy:'h0}, '{other_status:'h284366, wel:'h0, busy:'h0}}
UVM_ERROR @ 3354127732 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xa10d99) != exp '{'{other_status:'h284366, wel:'h0, busy:'h0}, '{other_status:'h284366, wel:'h0, busy:'h0}}
UVM_INFO @ 5263327732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.spi_device_flash_all.60783651283742085728043691356368446967193647632192934493022833521397999459833
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/41.spi_device_flash_all/latest/run.log
UVM_ERROR @ 1781425790 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x84cdb5) != exp '{'{other_status:'h21336d, wel:'h0, busy:'h0}, '{other_status:'h21336d, wel:'h0, busy:'h0}}
UVM_FATAL @ 1782279944 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1782279944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more tests.
UVM_FATAL (spi_device_scoreboard.sv:726) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 16 failures:
7.spi_device_flash_all.15949269578959885583932340788631647788419272507606015913659140142322931571603
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_flash_all/latest/run.log
UVM_FATAL @ 5395598789 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 5395598789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.spi_device_flash_all.21903239951258761600614442442564154041936456801193803480783811468686110479323
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_flash_all/latest/run.log
UVM_FATAL @ 110675959 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 110675959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
11.spi_device_flash_and_tpm.114546033698331741605333799449929560160601521870040386239029000982649312423785
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 141802175 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 141802175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.spi_device_flash_and_tpm.99870407069778590749278963998616850397830927589365950019751687750212310015007
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 46087160409 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 46087160409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
14.spi_device_upload.38594743103208606632747412740101860845548840201440225779522211565002980606539
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/14.spi_device_upload/latest/run.log
UVM_FATAL @ 1898101356 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1898101356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.spi_device_upload.3477891067970925433899223512981564896435565255459306779987318426548184177147
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/29.spi_device_upload/latest/run.log
UVM_FATAL @ 168205257 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 168205257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
28.spi_device_stress_all.79832515304333347756590162280541808723586379586947628644054872346962693456584
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/28.spi_device_stress_all/latest/run.log
UVM_FATAL @ 300126650 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 300126650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.spi_device_stress_all.71057624879651845503436105669289408021274429572629088374763708677907593932621
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/40.spi_device_stress_all/latest/run.log
UVM_FATAL @ 126542999 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 126542999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 3 failures:
Test spi_device_cfg_cmd has 1 failures.
13.spi_device_cfg_cmd.8185834321803195246651983019316067826096355451872718023305974117300070274401
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 63930161 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x76d07e) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h1db41f, wel:'h0, busy:'h0}, '{other_status:'h1db41f, wel:'h0, busy:'h0}}
UVM_ERROR @ 64021997 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x76d07e) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h1db41f, wel:'h0, busy:'h0}, '{other_status:'h1db41f, wel:'h0, busy:'h0}}
UVM_ERROR @ 64573013 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x76d07e) != exp '{'{other_status:'h1db41f, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h1db41f, wel:'h0, busy:'h0}, '{other_status:'h1db41f, wel:'h0, busy:'h0}}
UVM_INFO @ 64756685 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 1, test op = 0x4
UVM_ERROR @ 65042397 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x76d07e) != exp '{'{other_status:'h1db41f, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h1db41f, wel:'h0, busy:'h0}, '{other_status:'h1db41f, wel:'h0, busy:'h0}}
Test spi_device_stress_all has 1 failures.
45.spi_device_stress_all.47666113489176747874036899069884975335795910283599523078537456348523725603828
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_stress_all/latest/run.log
UVM_ERROR @ 265942125 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h2a4493, wel:'h0, busy:'h0}}
UVM_FATAL @ 5056994001 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 5056994001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_flash_and_tpm has 1 failures.
49.spi_device_flash_and_tpm.57306972412659901052048627154960636918142100655453861131406515267336390181492
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 50218878 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3927ae, wel:'h0, busy:'h0}}
UVM_ERROR @ 398282099 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe49eba) != exp '{'{other_status:'h3927ae, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3927ae, wel:'h0, busy:'h0}, '{other_status:'h3927ae, wel:'h0, busy:'h0}}
UVM_ERROR @ 963715195 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR @ 964215211 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR @ 964715227 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:
25.spi_device_flash_all.36210992247719952767587123885803407914625822653638368678953208404419890951723
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/25.spi_device_flash_all/latest/run.log
UVM_ERROR @ 9002142367 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xf56012) != exp '{'{other_status:'h3d5804, wel:'h0, busy:'h0}, '{other_status:'h3b8c66, wel:'h0, busy:'h0}, '{other_status:'h3d5804, wel:'h0, busy:'h0}, '{other_status:'h3d5804, wel:'h0, busy:'h0}}
UVM_INFO @ 9007182367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---