SPI_DEVICE/2P Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: 0cb61fc7e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 1.128m 16.120ms 1 50 2.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.460s 49.789us 5 5 100.00
V1 csr_rw spi_device_csr_rw 2.750s 111.364us 20 20 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 33.460s 1.069ms 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 20.670s 1.260ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 3.870s 162.873us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.750s 111.364us 20 20 100.00
spi_device_csr_aliasing 20.670s 1.260ms 5 5 100.00
V1 mem_walk spi_device_mem_walk 0.690s 34.218us 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 2.180s 63.444us 5 5 100.00
V1 TOTAL 66 115 57.39
V2 csb_read spi_device_csb_read 0.860s 20.813us 50 50 100.00
V2 mem_parity spi_device_mem_parity 1.090s 64.101us 20 20 100.00
V2 mem_cfg spi_device_ram_cfg 0.750s 32.335us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 9.900s 927.417us 50 50 100.00
V2 tpm_write spi_device_tpm_rw 9.900s 927.417us 50 50 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 30.910s 10.589ms 50 50 100.00
spi_device_tpm_sts_read 1.110s 139.016us 50 50 100.00
V2 tpm_fully_random_case spi_device_tpm_all 1.091m 13.291ms 50 50 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 44.100s 20.139ms 50 50 100.00
spi_device_flash_all 17.560s 9.007ms 0 50 0.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 28.650s 40.131ms 50 50 100.00
spi_device_flash_all 17.560s 9.007ms 0 50 0.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 28.650s 40.131ms 50 50 100.00
spi_device_flash_all 17.560s 9.007ms 0 50 0.00
V2 cmd_info_slots spi_device_flash_all 17.560s 9.007ms 0 50 0.00
V2 cmd_read_status spi_device_intercept 32.550s 3.315ms 46 50 92.00
spi_device_flash_all 17.560s 9.007ms 0 50 0.00
V2 cmd_read_jedec spi_device_intercept 32.550s 3.315ms 46 50 92.00
spi_device_flash_all 17.560s 9.007ms 0 50 0.00
V2 cmd_read_sfdp spi_device_intercept 32.550s 3.315ms 46 50 92.00
spi_device_flash_all 17.560s 9.007ms 0 50 0.00
V2 cmd_fast_read spi_device_intercept 32.550s 3.315ms 46 50 92.00
spi_device_flash_all 17.560s 9.007ms 0 50 0.00
V2 cmd_read_pipeline spi_device_intercept 32.550s 3.315ms 46 50 92.00
spi_device_flash_all 17.560s 9.007ms 0 50 0.00
V2 flash_cmd_upload spi_device_upload 37.310s 46.105ms 36 50 72.00
V2 mailbox_command spi_device_mailbox 2.779m 40.086ms 46 50 92.00
V2 mailbox_cross_outside_command spi_device_mailbox 2.779m 40.086ms 46 50 92.00
V2 mailbox_cross_inside_command spi_device_mailbox 2.779m 40.086ms 46 50 92.00
V2 cmd_read_buffer spi_device_flash_mode 2.543m 10.551ms 39 50 78.00
spi_device_read_buffer_direct 22.840s 7.038ms 50 50 100.00
V2 cmd_dummy_cycle spi_device_mailbox 2.779m 40.086ms 46 50 92.00
spi_device_flash_all 17.560s 9.007ms 0 50 0.00
V2 quad_spi spi_device_flash_all 17.560s 9.007ms 0 50 0.00
V2 dual_spi spi_device_flash_all 17.560s 9.007ms 0 50 0.00
V2 4b_3b_feature spi_device_cfg_cmd 40.700s 11.209ms 25 50 50.00
V2 write_enable_disable spi_device_cfg_cmd 40.700s 11.209ms 25 50 50.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 1.128m 16.120ms 1 50 2.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 43.990s 5.057ms 0 50 0.00
V2 stress_all spi_device_stress_all 22.380s 5.057ms 11 50 22.00
V2 alert_test spi_device_alert_test 0.760s 13.843us 50 50 100.00
V2 intr_test spi_device_intr_test 0.800s 21.177us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 5.200s 210.034us 20 20 100.00
V2 tl_d_illegal_access spi_device_tl_errors 5.200s 210.034us 20 20 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.460s 49.789us 5 5 100.00
spi_device_csr_rw 2.750s 111.364us 20 20 100.00
spi_device_csr_aliasing 20.670s 1.260ms 5 5 100.00
spi_device_same_csr_outstanding 4.770s 166.136us 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.460s 49.789us 5 5 100.00
spi_device_csr_rw 2.750s 111.364us 20 20 100.00
spi_device_csr_aliasing 20.670s 1.260ms 5 5 100.00
spi_device_same_csr_outstanding 4.770s 166.136us 20 20 100.00
V2 TOTAL 764 961 79.50
V2S tl_intg_err spi_device_sec_cm 1.230s 232.490us 5 5 100.00
spi_device_tl_intg_err 22.420s 993.861us 20 20 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 22.420s 993.861us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 855 1101 77.66

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 22 22 14 63.64
V2S 2 2 2 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
92.21 97.67 93.04 98.61 80.85 96.09 90.90 88.33

Failure Buckets

Past Results