ecd9f08747| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_flash_and_tpm | 34.610s | 19.857ms | 0 | 50 | 0.00 |
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.540s | 75.206us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_device_csr_rw | 2.720s | 432.500us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 39.630s | 20.878ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_device_csr_aliasing | 23.960s | 1.073ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 4.380s | 179.073us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 2.720s | 432.500us | 20 | 20 | 100.00 |
| spi_device_csr_aliasing | 23.960s | 1.073ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_device_mem_walk | 0.680s | 14.090us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_device_mem_partial_access | 1.900s | 110.993us | 5 | 5 | 100.00 |
| V1 | TOTAL | 65 | 115 | 56.52 | |||
| V2 | csb_read | spi_device_csb_read | 0.850s | 21.034us | 50 | 50 | 100.00 |
| V2 | mem_parity | spi_device_mem_parity | 1.130s | 441.180us | 20 | 20 | 100.00 |
| V2 | mem_cfg | spi_device_ram_cfg | 0.790s | 15.825us | 1 | 1 | 100.00 |
| V2 | tpm_read | spi_device_tpm_rw | 13.740s | 334.324us | 50 | 50 | 100.00 |
| V2 | tpm_write | spi_device_tpm_rw | 13.740s | 334.324us | 50 | 50 | 100.00 |
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 35.520s | 11.987ms | 50 | 50 | 100.00 |
| spi_device_tpm_sts_read | 1.110s | 280.498us | 50 | 50 | 100.00 | ||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 57.990s | 44.340ms | 50 | 50 | 100.00 |
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 41.280s | 15.414ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 8.110s | 916.168us | 0 | 50 | 0.00 | ||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 40.300s | 55.002ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 8.110s | 916.168us | 0 | 50 | 0.00 | ||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 40.300s | 55.002ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 8.110s | 916.168us | 0 | 50 | 0.00 | ||
| V2 | cmd_info_slots | spi_device_flash_all | 8.110s | 916.168us | 0 | 50 | 0.00 |
| V2 | cmd_read_status | spi_device_intercept | 27.630s | 30.749ms | 45 | 50 | 90.00 |
| spi_device_flash_all | 8.110s | 916.168us | 0 | 50 | 0.00 | ||
| V2 | cmd_read_jedec | spi_device_intercept | 27.630s | 30.749ms | 45 | 50 | 90.00 |
| spi_device_flash_all | 8.110s | 916.168us | 0 | 50 | 0.00 | ||
| V2 | cmd_read_sfdp | spi_device_intercept | 27.630s | 30.749ms | 45 | 50 | 90.00 |
| spi_device_flash_all | 8.110s | 916.168us | 0 | 50 | 0.00 | ||
| V2 | cmd_fast_read | spi_device_intercept | 27.630s | 30.749ms | 45 | 50 | 90.00 |
| spi_device_flash_all | 8.110s | 916.168us | 0 | 50 | 0.00 | ||
| V2 | cmd_read_pipeline | spi_device_intercept | 27.630s | 30.749ms | 45 | 50 | 90.00 |
| spi_device_flash_all | 8.110s | 916.168us | 0 | 50 | 0.00 | ||
| V2 | flash_cmd_upload | spi_device_upload | 49.280s | 95.537ms | 35 | 50 | 70.00 |
| V2 | mailbox_command | spi_device_mailbox | 4.391m | 61.120ms | 43 | 50 | 86.00 |
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 4.391m | 61.120ms | 43 | 50 | 86.00 |
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 4.391m | 61.120ms | 43 | 50 | 86.00 |
| V2 | cmd_read_buffer | spi_device_flash_mode | 5.019m | 36.587ms | 40 | 50 | 80.00 |
| spi_device_read_buffer_direct | 22.980s | 2.283ms | 50 | 50 | 100.00 | ||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 4.391m | 61.120ms | 43 | 50 | 86.00 |
| spi_device_flash_all | 8.110s | 916.168us | 0 | 50 | 0.00 | ||
| V2 | quad_spi | spi_device_flash_all | 8.110s | 916.168us | 0 | 50 | 0.00 |
| V2 | dual_spi | spi_device_flash_all | 8.110s | 916.168us | 0 | 50 | 0.00 |
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 36.040s | 10.135ms | 21 | 50 | 42.00 |
| V2 | write_enable_disable | spi_device_cfg_cmd | 36.040s | 10.135ms | 21 | 50 | 42.00 |
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 34.610s | 19.857ms | 0 | 50 | 0.00 |
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 14.290s | 4.926ms | 0 | 50 | 0.00 |
| V2 | stress_all | spi_device_stress_all | 14.930s | 987.527us | 10 | 50 | 20.00 |
| V2 | alert_test | spi_device_alert_test | 0.790s | 35.009us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_device_intr_test | 0.800s | 38.169us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 4.800s | 211.214us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_device_tl_errors | 4.800s | 211.214us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.540s | 75.206us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.720s | 432.500us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 23.960s | 1.073ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.620s | 867.193us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.540s | 75.206us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.720s | 432.500us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 23.960s | 1.073ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.620s | 867.193us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 755 | 961 | 78.56 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 1.220s | 662.717us | 5 | 5 | 100.00 |
| spi_device_tl_intg_err | 25.010s | 8.941ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 25.010s | 8.941ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 845 | 1101 | 76.75 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 22 | 22 | 14 | 63.64 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 92.15 | 97.67 | 93.02 | 98.61 | 80.85 | 96.09 | 90.90 | 87.88 |
Job spi_device_2p-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 219 failures:
0.spi_device_flash_mode.32759960576460712471231530725586430658737626141023404430807493998159545528861
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_mode/latest/run.log
Job ID: smart:2021bc14-d8c1-4834-aef7-26eebaf285d4
1.spi_device_flash_mode.937379310972317405007674622375019029038388222788517945456816300642588408590
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_mode/latest/run.log
Job ID: smart:af84c2b1-61f0-40e9-9051-851043e2bdf1
... and 8 more failures.
0.spi_device_flash_all.46186217525270003443682661830726570827498351348839737438500214404360266290824
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_all/latest/run.log
Job ID: smart:269353a4-ada0-45e0-81bf-d5a8906c7c84
1.spi_device_flash_all.38368283691711578457677200475544265630039734076655335641079592052944993330741
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_all/latest/run.log
Job ID: smart:c536d184-1520-413e-b4ac-5325b625cadc
... and 47 more failures.
0.spi_device_flash_and_tpm.8164097677102029957027916089729170921560752263636580932172837616184805317438
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:bdb49d57-6d2f-448e-b345-5926843df102
1.spi_device_flash_and_tpm.102925450330313222772277813077544874102380303398321446804079534976270084710940
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:56b63648-f582-49f0-bee9-4d6fb12504b0
... and 42 more failures.
0.spi_device_flash_and_tpm_min_idle.75192599747688897269743138444991872852080886505277370456802437920155030340662
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:e506c3b6-4d82-46a1-b0a6-0433d14614c2
1.spi_device_flash_and_tpm_min_idle.72128096570226176789158520284574846269802595932809139699808449335691630603087
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:58e71571-6b4a-41e8-a43f-fc633ba5ff33
... and 47 more failures.
0.spi_device_stress_all.94726012457947520550955436712868220114629794407961346192144871312656179162468
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_stress_all/latest/run.log
Job ID: smart:acedb790-3710-461c-bd39-2ee56700bc60
1.spi_device_stress_all.49024258128988686059693335271698861802009747755995164130272187208607047698998
Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_stress_all/latest/run.log
Job ID: smart:1d96abf3-759f-47b6-ad05-42cb73bda7ff
... and 36 more failures.
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 23 failures:
Test spi_device_cfg_cmd has 11 failures.
1.spi_device_cfg_cmd.64738192636086221959477814065528417088806713025389524325849143711384181606940
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 22174486 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 22644486 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 22794486 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 23324486 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 23554486 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 1, test op = 0xb7
2.spi_device_cfg_cmd.93201854135145006698267663424026655890671380264541131675306439733173436360134
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 116008393 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xb7dbe) != exp '{'{other_status:'h2df6f, wel:'h0, busy:'h0}, '{other_status:'h2df6f, wel:'h0, busy:'h0}}
UVM_ERROR @ 116518393 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xb7dbe) != exp '{'{other_status:'h2df6f, wel:'h0, busy:'h0}, '{other_status:'h2df6f, wel:'h0, busy:'h0}}
UVM_INFO @ 116738393 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 4, test op = 0x6
UVM_ERROR @ 116948393 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xb7dbe) != exp '{'{other_status:'h2df6f, wel:'h0, busy:'h0}, '{other_status:'h2df6f, wel:'h0, busy:'h0}}
UVM_ERROR @ 117408393 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xb7dbe) != exp '{'{other_status:'h2df6f, wel:'h0, busy:'h0}, '{other_status:'h2df6f, wel:'h0, busy:'h0}}
... and 9 more failures.
Test spi_device_upload has 8 failures.
3.spi_device_upload.73723678896826455301913752279812190818944257809515306999732631784449923256907
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_upload/latest/run.log
UVM_ERROR @ 612104985 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 614424448 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 615451928 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 4, test op = 0x8f
UVM_INFO @ 653799459 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 5, test op = 0x68
UVM_ERROR @ 775078511 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
18.spi_device_upload.25068712991479966217470344378683239995842825259430259186323943383030048481836
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_upload/latest/run.log
UVM_ERROR @ 2252797430 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 2260287166 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 2262301722 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 6, test op = 0xb
UVM_INFO @ 2433620678 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 7, test op = 0x15
UVM_INFO @ 4402494558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
... and 6 more failures.
Test spi_device_stress_all has 1 failures.
10.spi_device_stress_all.35164807889729847991978794498491192852107644303276107410641433076583867150416
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_stress_all/latest/run.log
UVM_ERROR @ 36329897 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 462135189 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/5
UVM_INFO @ 584857866 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/5
UVM_INFO @ 727227005 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 4/5
UVM_INFO @ 852803940 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 5/5
Test spi_device_flash_and_tpm has 2 failures.
20.spi_device_flash_and_tpm.60547867950879555133803741265407221393435455475625092305507121135354168686768
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/20.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 2973691792 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe3d579) != exp '{'{other_status:'h38f55e, wel:'h0, busy:'h0}, '{other_status:'h38f55e, wel:'h0, busy:'h0}}
UVM_FATAL @ 2979433930 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2979433930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.spi_device_flash_and_tpm.60493141566776967189898699103248543296743012452461056832052395675399398003040
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/49.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 550919038 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 566893317 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 566893317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_flash_and_tpm_min_idle has 1 failures.
32.spi_device_flash_and_tpm_min_idle.9841122514759130487815354412704181975481164381142086323699438774505683664396
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/32.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 4798601055 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x9cbff5) != exp '{'{other_status:'h272ffd, wel:'h0, busy:'h0}, '{other_status:'h272ffd, wel:'h0, busy:'h0}}
UVM_FATAL @ 4926402340 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 4926402340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (spi_device_scoreboard.sv:726) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 12 failures:
Test spi_device_upload has 7 failures.
1.spi_device_upload.56394709227462173231299628252356495017581784425322565196671515934838373360563
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_upload/latest/run.log
UVM_FATAL @ 1468391058 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1468391058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.spi_device_upload.72123601626722167201059385637973459347123701663876619223238782645664861552353
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_upload/latest/run.log
UVM_FATAL @ 512131941 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 512131941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Test spi_device_flash_all has 1 failures.
10.spi_device_flash_all.34564652371113552731431338079348226444605052976049049956249487995362940812490
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_flash_all/latest/run.log
UVM_FATAL @ 916167604 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 916167604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_stress_all has 1 failures.
23.spi_device_stress_all.13057888311519830736501745289560650841388406593833558865690971303655750812732
Line 260, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/23.spi_device_stress_all/latest/run.log
UVM_FATAL @ 170267710 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 170267710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_flash_and_tpm has 3 failures.
27.spi_device_flash_and_tpm.9883920617603563503313885104153792112029897738365756950078375618756503689033
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/27.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 3310747235 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 3310747235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.spi_device_flash_and_tpm.38454960733439993027401168244779862990773773293719610784553196448181543490658
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/42.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 19856934101 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 19856934101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:
4.spi_device_cfg_cmd.4148639085406135282812689465547625061563451966234555266344538093230401299974
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 49187608 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xabe5a) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h2a62c8, wel:'h0, busy:'h0}, '{other_status:'h2af96, wel:'h0, busy:'h0}, '{other_status:'h2af96, wel:'h0, busy:'h0}}
UVM_ERROR @ 49562602 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xabe5a) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h2a62c8, wel:'h0, busy:'h0}, '{other_status:'h2af96, wel:'h0, busy:'h0}, '{other_status:'h2af96, wel:'h0, busy:'h0}}
UVM_ERROR @ 49979262 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xabe5a) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h2a62c8, wel:'h0, busy:'h0}, '{other_status:'h2af96, wel:'h0, busy:'h0}, '{other_status:'h2af96, wel:'h0, busy:'h0}}
UVM_ERROR @ 50125093 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xabe5a) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h2a62c8, wel:'h0, busy:'h0}, '{other_status:'h2af96, wel:'h0, busy:'h0}, '{other_status:'h2af96, wel:'h0, busy:'h0}}
UVM_ERROR @ 50500087 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xabe5a) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h2a62c8, wel:'h0, busy:'h0}, '{other_status:'h2af96, wel:'h0, busy:'h0}, '{other_status:'h2af96, wel:'h0, busy:'h0}}
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:
47.spi_device_flash_and_tpm.84305730427584127741309386087543042290981807132706651399417005217138755662668
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 1120670399 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h265b9c, wel:'h0, busy:'h0}, '{other_status:'h265b9c, wel:'h0, busy:'h0}}
UVM_INFO @ 1251274695 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/3
UVM_FATAL @ 1301559495 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1301559495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---