SPI_DEVICE/2P Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: `d0c52cdadd`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	30.480s	2.421ms	0	50	0.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.340s	44.398us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.870s	494.253us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	33.740s	1.045ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.940s	2.718ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.730s	139.042us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.870s	494.253us	20	20	100.00
		spi_device_csr_aliasing	24.940s	2.718ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.740s	24.433us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.200s	275.930us	5	5	100.00
V1		TOTAL			65	115	56.52
V2	csb_read	spi_device_csb_read	0.880s	15.032us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.110s	424.000us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.700s	28.232us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	14.660s	3.063ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	14.660s	3.063ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	29.370s	40.669ms	50	50	100.00
		spi_device_tpm_sts_read	1.200s	302.981us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.149m	59.435ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	34.360s	44.355ms	50	50	100.00
		spi_device_flash_all	10.090s	16.315ms	0	50	0.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	58.880s	273.951ms	50	50	100.00
		spi_device_flash_all	10.090s	16.315ms	0	50	0.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	58.880s	273.951ms	50	50	100.00
		spi_device_flash_all	10.090s	16.315ms	0	50	0.00
V2	cmd_info_slots	spi_device_flash_all	10.090s	16.315ms	0	50	0.00
V2	cmd_read_status	spi_device_intercept	48.620s	18.754ms	44	50	88.00
		spi_device_flash_all	10.090s	16.315ms	0	50	0.00
V2	cmd_read_jedec	spi_device_intercept	48.620s	18.754ms	44	50	88.00
		spi_device_flash_all	10.090s	16.315ms	0	50	0.00
V2	cmd_read_sfdp	spi_device_intercept	48.620s	18.754ms	44	50	88.00
		spi_device_flash_all	10.090s	16.315ms	0	50	0.00
V2	cmd_fast_read	spi_device_intercept	48.620s	18.754ms	44	50	88.00
		spi_device_flash_all	10.090s	16.315ms	0	50	0.00
V2	cmd_read_pipeline	spi_device_intercept	48.620s	18.754ms	44	50	88.00
		spi_device_flash_all	10.090s	16.315ms	0	50	0.00
V2	flash_cmd_upload	spi_device_upload	51.130s	66.429ms	39	50	78.00
V2	mailbox_command	spi_device_mailbox	2.980m	43.548ms	43	50	86.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.980m	43.548ms	43	50	86.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.980m	43.548ms	43	50	86.00
V2	cmd_read_buffer	spi_device_flash_mode	2.099m	9.048ms	40	50	80.00
		spi_device_read_buffer_direct	21.260s	4.667ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.980m	43.548ms	43	50	86.00
		spi_device_flash_all	10.090s	16.315ms	0	50	0.00
V2	quad_spi	spi_device_flash_all	10.090s	16.315ms	0	50	0.00
V2	dual_spi	spi_device_flash_all	10.090s	16.315ms	0	50	0.00
V2	4b_3b_feature	spi_device_cfg_cmd	28.360s	3.384ms	16	50	32.00
V2	write_enable_disable	spi_device_cfg_cmd	28.360s	3.384ms	16	50	32.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	30.480s	2.421ms	0	50	0.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	19.910s	1.986ms	0	50	0.00
V2	stress_all	spi_device_stress_all	10.780s	977.396us	10	50	20.00
V2	alert_test	spi_device_alert_test	0.840s	17.302us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.780s	23.995us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.360s	1.027ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.360s	1.027ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.340s	44.398us	5	5	100.00
		spi_device_csr_rw	2.870s	494.253us	20	20	100.00
		spi_device_csr_aliasing	24.940s	2.718ms	5	5	100.00
		spi_device_same_csr_outstanding	4.420s	563.433us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.340s	44.398us	5	5	100.00
		spi_device_csr_rw	2.870s	494.253us	20	20	100.00
		spi_device_csr_aliasing	24.940s	2.718ms	5	5	100.00
		spi_device_same_csr_outstanding	4.420s	563.433us	20	20	100.00
V2		TOTAL			753	961	78.36
V2S	tl_intg_err	spi_device_sec_cm	1.210s	1.415ms	5	5	100.00
		spi_device_tl_intg_err	23.130s	10.812ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.130s	10.812ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			843	1101	76.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	22	22	14	63.64
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.10	97.54	92.90	98.61	80.85	95.95	90.90	87.93

Failure Buckets

Job spi_device_2p-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 224 failures:
- Test spi_device_flash_all has 48 failures.
  - 0.spi_device_flash_all.32477674172478105008191598883124978160500430109701108315765932700424159061805
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_all/latest/run.log
```
  Job ID: smart:30a7cfd1-0b5e-44a5-bed6-6fcd60ced097
```
  - 1.spi_device_flash_all.105447306120711087107660893927559768490681302234554228460618251840362568513428
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_all/latest/run.log
```
  Job ID: smart:08365db5-90f2-40b1-bebc-5c0321d6cfb9
```
  - ... and 46 more failures.
- Test spi_device_flash_and_tpm has 45 failures.
  - 0.spi_device_flash_and_tpm.67640475470648762853610246537163414109857305507489493062673162084380632909890
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log
```
  Job ID: smart:d0609f9f-15c4-48a7-ae7e-9147667c4d21
```
  - 1.spi_device_flash_and_tpm.512571159510072866468209930078877953784469391047276921237036871223532760442
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log
```
  Job ID: smart:0cf25956-f668-416b-ad79-714a5a01f36a
```
  - ... and 43 more failures.
- Test spi_device_flash_and_tpm_min_idle has 45 failures.
  - 0.spi_device_flash_and_tpm_min_idle.9036366616658842094587018237584404934734670493545663555321291238019266404133
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  Job ID: smart:1c57ae18-0cb0-4afd-95f6-e078aaffe61d
```
  - 1.spi_device_flash_and_tpm_min_idle.38556983219100339035661071033683244940375687444854014961838666206681730119662
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  Job ID: smart:2ff9a295-4ce4-4aba-bea2-d7d623ad624d
```
  - ... and 43 more failures.
- Test spi_device_stress_all has 38 failures.
  - 0.spi_device_stress_all.36437153275909171988780916907687560412987404317352803758605836765353726973098
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_stress_all/latest/run.log
```
  Job ID: smart:bb9fe7de-8025-4046-908c-b631668c23ec
```
  - 3.spi_device_stress_all.46238096425302437863590744124393947393087571382676194927200556764829023539644
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_stress_all/latest/run.log
```
  Job ID: smart:856def2f-ad63-4e72-bdb5-4f788bec8aa3
```
  - ... and 36 more failures.
- Test spi_device_mailbox has 7 failures.
  - 1.spi_device_mailbox.105226502830892783076142322638678285815132547237592735039295669872745863470572
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_mailbox/latest/run.log
```
  Job ID: smart:cb23a96d-7de5-4ed6-a2cf-2e07ce327d83
```
  - 9.spi_device_mailbox.93180080940152691548836826813897257265150084934590923827748637292924618240741
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_mailbox/latest/run.log
```
  Job ID: smart:8da3b53e-e207-439f-b482-d50b046c31db
```
  - ... and 5 more failures.
- ... and 3 more tests.

UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 19 failures:

Test spi_device_upload has 9 failures.

2.spi_device_upload.48728532959452969764106203023359260499679770781609042356450874711648992972275
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_upload/latest/run.log

  UVM_ERROR @ 403418544 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 611567563 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_INFO @ 613675818 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 2, test op = 0x2f
  UVM_ERROR @ 694823047 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 765511860 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}

9.spi_device_upload.57982774900852685298492018155998720744212431019685277254088706638138906352327
Line 257, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_upload/latest/run.log

  UVM_ERROR @ 137007592 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 137607592 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 137767592 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 137767592 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_ERROR @ 138517592 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}

... and 7 more failures.

Test spi_device_cfg_cmd has 6 failures.

2.spi_device_cfg_cmd.38006829386122916349736598664520850122128121650721665524141642706485004571304
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 187799918 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x703abe) != exp '{'{other_status:'h1c0eaf, wel:'h0, busy:'h0}, '{other_status:'h1c0eaf, wel:'h0, busy:'h0}}
  UVM_ERROR @ 187987415 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x703abe) != exp '{'{other_status:'h1c0eaf, wel:'h0, busy:'h0}, '{other_status:'h1c0eaf, wel:'h0, busy:'h0}}
  UVM_ERROR @ 188174912 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x703abe) != exp '{'{other_status:'h1c0eaf, wel:'h0, busy:'h0}, '{other_status:'h1c0eaf, wel:'h0, busy:'h0}}
  UVM_ERROR @ 188945733 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x703abe) != exp '{'{other_status:'h1c0eaf, wel:'h0, busy:'h0}, '{other_status:'h1c0eaf, wel:'h0, busy:'h0}}
  UVM_ERROR @ 189049898 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x703abe) != exp '{'{other_status:'h1c0eaf, wel:'h0, busy:'h0}, '{other_status:'h1c0eaf, wel:'h0, busy:'h0}}

7.spi_device_cfg_cmd.111189623227471408980837938180255798912370654018914802581426496463350469985078
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 1013334689 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x5764e2) != exp '{'{other_status:'h15d938, wel:'h0, busy:'h0}, '{other_status:'h15d938, wel:'h0, busy:'h0}}
  UVM_ERROR @ 1017001341 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x5764e2) != exp '{'{other_status:'h15d938, wel:'h0, busy:'h0}, '{other_status:'h15d938, wel:'h0, busy:'h0}}
  UVM_INFO @ 1018001337 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 2, test op = 0xb7
  UVM_ERROR @ 1021917988 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x5764e2) != exp '{'{other_status:'h15d938, wel:'h0, busy:'h0}, '{other_status:'h15d938, wel:'h0, busy:'h0}}
  UVM_ERROR @ 1023251316 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x5764e2) != exp '{'{other_status:'h15d938, wel:'h0, busy:'h0}, '{other_status:'h15d938, wel:'h0, busy:'h0}}

... and 4 more failures.

Test spi_device_flash_and_tpm_min_idle has 2 failures.

2.spi_device_flash_and_tpm_min_idle.59576392398466351056781648253264696938784873649011336825769090713866336227168
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 5577616354 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_FATAL @ 5678385142 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 5678385142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.spi_device_flash_and_tpm_min_idle.12002284388680814254469858799083877001144208240355218197073185622332438623284
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/40.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 1726120212 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 1800420212 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 1899570212 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 1963060212 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x3) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_FATAL @ 1985818213 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])

Test spi_device_flash_all has 1 failures.

15.spi_device_flash_all.73069240739650349740013931681292066626621790270837037961022405295924225642565
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/15.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 260884362 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 283578418 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 303735708 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h118b32, wel:'h0, busy:'h0}}
  UVM_ERROR @ 325082436 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x462cca) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h118b32, wel:'h0, busy:'h0}, '{other_status:'h118b32, wel:'h0, busy:'h0}}
  UVM_ERROR @ 326103458 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x462cca) != exp '{'{other_status:'h118b32, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h118b32, wel:'h0, busy:'h0}, '{other_status:'h118b32, wel:'h0, busy:'h0}}

Test spi_device_flash_and_tpm has 1 failures.

44.spi_device_flash_and_tpm.31067620694101711122436368420071148706675160308905346371643986168883187731241
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/44.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 1180093596 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_FATAL @ 1192012765 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1192012765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (spi_device_scoreboard.sv:726) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 11 failures:

Test spi_device_upload has 2 failures.

7.spi_device_upload.101847914137738500035810099521729654753164262059226475277604738697463703478829
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_upload/latest/run.log

  UVM_FATAL @  87853487 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  87853487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.spi_device_upload.107065911991687478879140102346439028979725445513577421587552290240242875650008
Line 260, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/36.spi_device_upload/latest/run.log

  UVM_FATAL @ 2524514102 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 2524514102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_flash_and_tpm has 4 failures.

7.spi_device_flash_and_tpm.3196140351471054646575179081357076843458404422934836195641168183162907167992
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/7.spi_device_flash_and_tpm/latest/run.log

  UVM_FATAL @ 852631146 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 852631146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.spi_device_flash_and_tpm.73206564520679467563385016774762384455706693767906318426152339007783404925165
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/12.spi_device_flash_and_tpm/latest/run.log

  UVM_FATAL @ 523583415 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 523583415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test spi_device_stress_all has 2 failures.

8.spi_device_stress_all.59946703746565247729311299164162437807765697691176154907798030298391451426542
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/8.spi_device_stress_all/latest/run.log

  UVM_FATAL @ 977396351 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 977396351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.spi_device_stress_all.59861565579116181483536019368770992686600248402645351783637596720287417075586
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_stress_all/latest/run.log

  UVM_FATAL @ 1000018719 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1000018719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_flash_and_tpm_min_idle has 2 failures.

26.spi_device_flash_and_tpm_min_idle.16988090478674688135064284084694714206070211668645253056363373194129855405347
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_FATAL @ 993897089 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 993897089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.spi_device_flash_and_tpm_min_idle.97499072790933293436109981979183514851308001051207877868253974151637618387065
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_FATAL @ 235908330 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 235908330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_flash_all has 1 failures.

27.spi_device_flash_all.8711682257199332660648686320270754471362868002444265974825171408324129886055
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/27.spi_device_flash_all/latest/run.log

  UVM_FATAL @ 16314777775 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 16314777775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_cfg_cmd has 2 failures.

1.spi_device_cfg_cmd.109524593116932054786392679686208079389340979963885467919343388536298854730695
Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @  87262830 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2e6fce) != exp '{'{other_status:'h2e1e45, wel:'h0, busy:'h0}, '{other_status:'h23a492, wel:'h0, busy:'h0}, '{other_status:'hb9bf3, wel:'h0, busy:'h0}, '{other_status:'hb9bf3, wel:'h0, busy:'h0}}
  UVM_INFO @  92262830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.spi_device_cfg_cmd.76765187166635105102184727076359713104765740933260069772662628732573275714677
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/22.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 142223320 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc616fe) != exp '{'{other_status:'h3185bf, wel:'h0, busy:'h0}, '{other_status:'h1a0e44, wel:'h0, busy:'h0}, '{other_status:'h3185bf, wel:'h0, busy:'h0}, '{other_status:'h3185bf, wel:'h0, busy:'h0}}
  UVM_ERROR @ 158196277 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc616fe) != exp '{'{other_status:'h3185bf, wel:'h0, busy:'h0}, '{other_status:'h1a0e44, wel:'h0, busy:'h0}, '{other_status:'h3185bf, wel:'h0, busy:'h0}, '{other_status:'h3185bf, wel:'h0, busy:'h0}}
  UVM_INFO @ 163196277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_flash_and_tpm_min_idle has 1 failures.

6.spi_device_flash_and_tpm_min_idle.85653473534105400071265652161241226487753985641467939424734230095996643609224
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 633872357 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x84fef9) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h213fbe, wel:'h0, busy:'h0}, '{other_status:'h213fbe, wel:'h0, busy:'h0}}
  UVM_FATAL @ 642105025 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 642105025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_cfg_cmd has 1 failures.

26.spi_device_cfg_cmd.3697529924408278493703200012933662761095590279681302545307045381413997348219
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/26.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 149139126 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xdda64a) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h376992, wel:'h0, busy:'h0}, '{other_status:'h376992, wel:'h0, busy:'h0}}
  UVM_INFO @ 149424846 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 1, test op = 0xb7
  UVM_ERROR @ 150805826 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xdda64a) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h376992, wel:'h0, busy:'h0}, '{other_status:'h376992, wel:'h0, busy:'h0}}
  UVM_ERROR @ 150996306 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xdda64a) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h376992, wel:'h0, busy:'h0}, '{other_status:'h376992, wel:'h0, busy:'h0}}
  UVM_ERROR @ 151162976 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xdda64a) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h376992, wel:'h0, busy:'h0}, '{other_status:'h376992, wel:'h0, busy:'h0}}