SPI_DEVICE/2P Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: 18c8953cf1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 54.820s 62.553ms 0 50 0.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.430s 39.848us 5 5 100.00
V1 csr_rw spi_device_csr_rw 2.650s 168.018us 20 20 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 37.780s 8.581ms 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 24.240s 4.791ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 3.940s 160.442us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.650s 168.018us 20 20 100.00
spi_device_csr_aliasing 24.240s 4.791ms 5 5 100.00
V1 mem_walk spi_device_mem_walk 0.710s 41.429us 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 2.110s 113.650us 5 5 100.00
V1 TOTAL 65 115 56.52
V2 csb_read spi_device_csb_read 0.910s 73.648us 50 50 100.00
V2 mem_parity spi_device_mem_parity 1.120s 123.448us 20 20 100.00
V2 mem_cfg spi_device_ram_cfg 0.780s 19.963us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 8.960s 959.648us 50 50 100.00
V2 tpm_write spi_device_tpm_rw 8.960s 959.648us 50 50 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 30.820s 51.827ms 50 50 100.00
spi_device_tpm_sts_read 1.300s 234.113us 50 50 100.00
V2 tpm_fully_random_case spi_device_tpm_all 56.500s 22.449ms 50 50 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 42.610s 16.756ms 50 50 100.00
spi_device_flash_all 17.740s 7.431ms 0 50 0.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 52.670s 141.236ms 50 50 100.00
spi_device_flash_all 17.740s 7.431ms 0 50 0.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 52.670s 141.236ms 50 50 100.00
spi_device_flash_all 17.740s 7.431ms 0 50 0.00
V2 cmd_info_slots spi_device_flash_all 17.740s 7.431ms 0 50 0.00
V2 cmd_read_status spi_device_intercept 49.310s 20.701ms 44 50 88.00
spi_device_flash_all 17.740s 7.431ms 0 50 0.00
V2 cmd_read_jedec spi_device_intercept 49.310s 20.701ms 44 50 88.00
spi_device_flash_all 17.740s 7.431ms 0 50 0.00
V2 cmd_read_sfdp spi_device_intercept 49.310s 20.701ms 44 50 88.00
spi_device_flash_all 17.740s 7.431ms 0 50 0.00
V2 cmd_fast_read spi_device_intercept 49.310s 20.701ms 44 50 88.00
spi_device_flash_all 17.740s 7.431ms 0 50 0.00
V2 cmd_read_pipeline spi_device_intercept 49.310s 20.701ms 44 50 88.00
spi_device_flash_all 17.740s 7.431ms 0 50 0.00
V2 flash_cmd_upload spi_device_upload 39.180s 34.521ms 40 50 80.00
V2 mailbox_command spi_device_mailbox 3.138m 68.196ms 45 50 90.00
V2 mailbox_cross_outside_command spi_device_mailbox 3.138m 68.196ms 45 50 90.00
V2 mailbox_cross_inside_command spi_device_mailbox 3.138m 68.196ms 45 50 90.00
V2 cmd_read_buffer spi_device_flash_mode 2.639m 48.018ms 44 50 88.00
spi_device_read_buffer_direct 17.610s 2.421ms 50 50 100.00
V2 cmd_dummy_cycle spi_device_mailbox 3.138m 68.196ms 45 50 90.00
spi_device_flash_all 17.740s 7.431ms 0 50 0.00
V2 quad_spi spi_device_flash_all 17.740s 7.431ms 0 50 0.00
V2 dual_spi spi_device_flash_all 17.740s 7.431ms 0 50 0.00
V2 4b_3b_feature spi_device_cfg_cmd 24.110s 11.960ms 24 50 48.00
V2 write_enable_disable spi_device_cfg_cmd 24.110s 11.960ms 24 50 48.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 54.820s 62.553ms 0 50 0.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 38.760s 7.875ms 0 50 0.00
V2 stress_all spi_device_stress_all 1.112m 6.337ms 9 50 18.00
V2 alert_test spi_device_alert_test 0.790s 59.325us 50 50 100.00
V2 intr_test spi_device_intr_test 0.820s 43.973us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 5.450s 99.397us 20 20 100.00
V2 tl_d_illegal_access spi_device_tl_errors 5.450s 99.397us 20 20 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.430s 39.848us 5 5 100.00
spi_device_csr_rw 2.650s 168.018us 20 20 100.00
spi_device_csr_aliasing 24.240s 4.791ms 5 5 100.00
spi_device_same_csr_outstanding 4.520s 661.331us 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.430s 39.848us 5 5 100.00
spi_device_csr_rw 2.650s 168.018us 20 20 100.00
spi_device_csr_aliasing 24.240s 4.791ms 5 5 100.00
spi_device_same_csr_outstanding 4.520s 661.331us 20 20 100.00
V2 TOTAL 767 961 79.81
V2S tl_intg_err spi_device_sec_cm 1.240s 107.166us 5 5 100.00
spi_device_tl_intg_err 21.850s 3.517ms 20 20 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 21.850s 3.517ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 857 1101 77.84

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 22 22 14 63.64
V2S 2 2 2 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
92.11 97.55 92.91 98.61 80.85 95.97 90.90 87.98

Failure Buckets

Past Results