SPI_DEVICE/2P Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: 9656691e03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 14.392m 183.213ms 50 50 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.370s 79.891us 5 5 100.00
V1 csr_rw spi_device_csr_rw 2.750s 103.748us 20 20 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 36.820s 1.886ms 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 15.510s 2.523ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 3.860s 486.625us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.750s 103.748us 20 20 100.00
spi_device_csr_aliasing 15.510s 2.523ms 5 5 100.00
V1 mem_walk spi_device_mem_walk 0.690s 11.474us 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 2.180s 139.765us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 csb_read spi_device_csb_read 0.850s 42.208us 50 50 100.00
V2 mem_parity spi_device_mem_parity 1.160s 95.108us 20 20 100.00
V2 mem_cfg spi_device_ram_cfg 0.730s 16.311us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 6.770s 162.469us 50 50 100.00
V2 tpm_write spi_device_tpm_rw 6.770s 162.469us 50 50 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 25.360s 8.231ms 50 50 100.00
spi_device_tpm_sts_read 1.080s 261.747us 50 50 100.00
V2 tpm_fully_random_case spi_device_tpm_all 38.440s 15.683ms 50 50 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 31.350s 58.867ms 50 50 100.00
spi_device_flash_all 8.907m 73.742ms 50 50 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 28.640s 20.170ms 50 50 100.00
spi_device_flash_all 8.907m 73.742ms 50 50 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 28.640s 20.170ms 50 50 100.00
spi_device_flash_all 8.907m 73.742ms 50 50 100.00
V2 cmd_info_slots spi_device_flash_all 8.907m 73.742ms 50 50 100.00
V2 cmd_read_status spi_device_intercept 20.230s 7.832ms 50 50 100.00
spi_device_flash_all 8.907m 73.742ms 50 50 100.00
V2 cmd_read_jedec spi_device_intercept 20.230s 7.832ms 50 50 100.00
spi_device_flash_all 8.907m 73.742ms 50 50 100.00
V2 cmd_read_sfdp spi_device_intercept 20.230s 7.832ms 50 50 100.00
spi_device_flash_all 8.907m 73.742ms 50 50 100.00
V2 cmd_fast_read spi_device_intercept 20.230s 7.832ms 50 50 100.00
spi_device_flash_all 8.907m 73.742ms 50 50 100.00
V2 cmd_read_pipeline spi_device_intercept 20.230s 7.832ms 50 50 100.00
spi_device_flash_all 8.907m 73.742ms 50 50 100.00
V2 flash_cmd_upload spi_device_upload 36.120s 12.239ms 50 50 100.00
V2 mailbox_command spi_device_mailbox 2.204m 29.182ms 50 50 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 2.204m 29.182ms 50 50 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 2.204m 29.182ms 50 50 100.00
V2 cmd_read_buffer spi_device_flash_mode 53.480s 42.893ms 50 50 100.00
spi_device_read_buffer_direct 20.340s 1.759ms 50 50 100.00
V2 cmd_dummy_cycle spi_device_mailbox 2.204m 29.182ms 50 50 100.00
spi_device_flash_all 8.907m 73.742ms 50 50 100.00
V2 quad_spi spi_device_flash_all 8.907m 73.742ms 50 50 100.00
V2 dual_spi spi_device_flash_all 8.907m 73.742ms 50 50 100.00
V2 4b_3b_feature spi_device_cfg_cmd 30.370s 2.175ms 50 50 100.00
V2 write_enable_disable spi_device_cfg_cmd 30.370s 2.175ms 50 50 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 14.392m 183.213ms 50 50 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 15.168m 364.325ms 50 50 100.00
V2 stress_all spi_device_stress_all 29.329m 711.913ms 50 50 100.00
V2 alert_test spi_device_alert_test 0.800s 30.605us 50 50 100.00
V2 intr_test spi_device_intr_test 0.800s 39.416us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 6.670s 230.205us 20 20 100.00
V2 tl_d_illegal_access spi_device_tl_errors 6.670s 230.205us 20 20 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.370s 79.891us 5 5 100.00
spi_device_csr_rw 2.750s 103.748us 20 20 100.00
spi_device_csr_aliasing 15.510s 2.523ms 5 5 100.00
spi_device_same_csr_outstanding 4.620s 884.817us 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.370s 79.891us 5 5 100.00
spi_device_csr_rw 2.750s 103.748us 20 20 100.00
spi_device_csr_aliasing 15.510s 2.523ms 5 5 100.00
spi_device_same_csr_outstanding 4.620s 884.817us 20 20 100.00
V2 TOTAL 961 961 100.00
V2S tl_intg_err spi_device_sec_cm 1.320s 157.118us 5 5 100.00
spi_device_tl_intg_err 21.870s 1.670ms 20 20 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 21.870s 1.670ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 1101 1101 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 22 22 22 100.00
V2S 2 2 2 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.94 98.35 94.21 98.61 89.36 97.14 95.81 98.12

Past Results