SPI_DEVICE/2P Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: 69c572b503

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 9.049m 54.104ms 50 50 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.370s 23.044us 5 5 100.00
V1 csr_rw spi_device_csr_rw 2.720s 102.324us 20 20 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 38.550s 10.792ms 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 21.920s 1.309ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 3.860s 217.438us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.720s 102.324us 20 20 100.00
spi_device_csr_aliasing 21.920s 1.309ms 5 5 100.00
V1 mem_walk spi_device_mem_walk 0.670s 29.716us 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 1.970s 53.215us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 csb_read spi_device_csb_read 0.860s 38.868us 50 50 100.00
V2 mem_parity spi_device_mem_parity 1.140s 26.226us 20 20 100.00
V2 mem_cfg spi_device_ram_cfg 0.790s 56.930us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 6.690s 828.517us 50 50 100.00
V2 tpm_write spi_device_tpm_rw 6.690s 828.517us 50 50 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 27.000s 18.434ms 50 50 100.00
spi_device_tpm_sts_read 1.000s 97.185us 50 50 100.00
V2 tpm_fully_random_case spi_device_tpm_all 50.920s 75.891ms 50 50 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 31.570s 112.539ms 50 50 100.00
spi_device_flash_all 9.288m 528.325ms 50 50 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 38.590s 58.743ms 50 50 100.00
spi_device_flash_all 9.288m 528.325ms 50 50 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 38.590s 58.743ms 50 50 100.00
spi_device_flash_all 9.288m 528.325ms 50 50 100.00
V2 cmd_info_slots spi_device_flash_all 9.288m 528.325ms 50 50 100.00
V2 cmd_read_status spi_device_intercept 40.090s 9.501ms 50 50 100.00
spi_device_flash_all 9.288m 528.325ms 50 50 100.00
V2 cmd_read_jedec spi_device_intercept 40.090s 9.501ms 50 50 100.00
spi_device_flash_all 9.288m 528.325ms 50 50 100.00
V2 cmd_read_sfdp spi_device_intercept 40.090s 9.501ms 50 50 100.00
spi_device_flash_all 9.288m 528.325ms 50 50 100.00
V2 cmd_fast_read spi_device_intercept 40.090s 9.501ms 50 50 100.00
spi_device_flash_all 9.288m 528.325ms 50 50 100.00
V2 cmd_read_pipeline spi_device_intercept 40.090s 9.501ms 50 50 100.00
spi_device_flash_all 9.288m 528.325ms 50 50 100.00
V2 flash_cmd_upload spi_device_upload 59.220s 77.632ms 50 50 100.00
V2 mailbox_command spi_device_mailbox 2.553m 15.184ms 50 50 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 2.553m 15.184ms 50 50 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 2.553m 15.184ms 50 50 100.00
V2 cmd_read_buffer spi_device_flash_mode 57.530s 4.099ms 50 50 100.00
spi_device_read_buffer_direct 17.540s 14.226ms 50 50 100.00
V2 cmd_dummy_cycle spi_device_mailbox 2.553m 15.184ms 50 50 100.00
spi_device_flash_all 9.288m 528.325ms 50 50 100.00
V2 quad_spi spi_device_flash_all 9.288m 528.325ms 50 50 100.00
V2 dual_spi spi_device_flash_all 9.288m 528.325ms 50 50 100.00
V2 4b_3b_feature spi_device_cfg_cmd 35.440s 3.326ms 50 50 100.00
V2 write_enable_disable spi_device_cfg_cmd 35.440s 3.326ms 50 50 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 9.049m 54.104ms 50 50 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 13.941m 383.778ms 50 50 100.00
V2 stress_all spi_device_stress_all 13.148m 121.376ms 50 50 100.00
V2 alert_test spi_device_alert_test 0.810s 15.413us 50 50 100.00
V2 intr_test spi_device_intr_test 0.820s 32.810us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 5.050s 275.218us 20 20 100.00
V2 tl_d_illegal_access spi_device_tl_errors 5.050s 275.218us 20 20 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.370s 23.044us 5 5 100.00
spi_device_csr_rw 2.720s 102.324us 20 20 100.00
spi_device_csr_aliasing 21.920s 1.309ms 5 5 100.00
spi_device_same_csr_outstanding 4.190s 639.901us 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.370s 23.044us 5 5 100.00
spi_device_csr_rw 2.720s 102.324us 20 20 100.00
spi_device_csr_aliasing 21.920s 1.309ms 5 5 100.00
spi_device_same_csr_outstanding 4.190s 639.901us 20 20 100.00
V2 TOTAL 961 961 100.00
V2S tl_intg_err spi_device_sec_cm 1.180s 89.869us 5 5 100.00
spi_device_tl_intg_err 18.560s 593.123us 20 20 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 18.560s 593.123us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 1101 1101 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 22 22 22 100.00
V2S 2 2 2 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.95 98.35 94.20 98.61 89.36 97.14 95.81 98.17

Past Results