SPI_DEVICE/2P Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: 00fe426038

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 11.191m 321.779ms 50 50 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.510s 187.955us 5 5 100.00
V1 csr_rw spi_device_csr_rw 2.830s 189.828us 20 20 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 40.950s 5.491ms 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 24.570s 2.895ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 4.260s 275.967us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.830s 189.828us 20 20 100.00
spi_device_csr_aliasing 24.570s 2.895ms 5 5 100.00
V1 mem_walk spi_device_mem_walk 0.700s 11.963us 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 2.080s 124.308us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 csb_read spi_device_csb_read 0.850s 29.495us 50 50 100.00
V2 mem_parity spi_device_mem_parity 1.100s 122.218us 20 20 100.00
V2 mem_cfg spi_device_ram_cfg 0.720s 46.712us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 12.810s 1.595ms 50 50 100.00
V2 tpm_write spi_device_tpm_rw 12.810s 1.595ms 50 50 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 22.110s 30.537ms 50 50 100.00
spi_device_tpm_sts_read 1.080s 77.076us 50 50 100.00
V2 tpm_fully_random_case spi_device_tpm_all 47.650s 9.558ms 50 50 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 36.800s 24.145ms 50 50 100.00
spi_device_flash_all 7.207m 227.386ms 50 50 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 29.390s 8.557ms 50 50 100.00
spi_device_flash_all 7.207m 227.386ms 50 50 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 29.390s 8.557ms 50 50 100.00
spi_device_flash_all 7.207m 227.386ms 50 50 100.00
V2 cmd_info_slots spi_device_flash_all 7.207m 227.386ms 50 50 100.00
V2 cmd_read_status spi_device_intercept 38.670s 4.622ms 50 50 100.00
spi_device_flash_all 7.207m 227.386ms 50 50 100.00
V2 cmd_read_jedec spi_device_intercept 38.670s 4.622ms 50 50 100.00
spi_device_flash_all 7.207m 227.386ms 50 50 100.00
V2 cmd_read_sfdp spi_device_intercept 38.670s 4.622ms 50 50 100.00
spi_device_flash_all 7.207m 227.386ms 50 50 100.00
V2 cmd_fast_read spi_device_intercept 38.670s 4.622ms 50 50 100.00
spi_device_flash_all 7.207m 227.386ms 50 50 100.00
V2 cmd_read_pipeline spi_device_intercept 38.670s 4.622ms 50 50 100.00
spi_device_flash_all 7.207m 227.386ms 50 50 100.00
V2 flash_cmd_upload spi_device_upload 43.220s 13.795ms 50 50 100.00
V2 mailbox_command spi_device_mailbox 1.847m 39.561ms 50 50 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 1.847m 39.561ms 50 50 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 1.847m 39.561ms 50 50 100.00
V2 cmd_read_buffer spi_device_flash_mode 1.531m 6.761ms 50 50 100.00
spi_device_read_buffer_direct 20.680s 6.701ms 50 50 100.00
V2 cmd_dummy_cycle spi_device_mailbox 1.847m 39.561ms 50 50 100.00
spi_device_flash_all 7.207m 227.386ms 50 50 100.00
V2 quad_spi spi_device_flash_all 7.207m 227.386ms 50 50 100.00
V2 dual_spi spi_device_flash_all 7.207m 227.386ms 50 50 100.00
V2 4b_3b_feature spi_device_cfg_cmd 21.060s 25.752ms 50 50 100.00
V2 write_enable_disable spi_device_cfg_cmd 21.060s 25.752ms 50 50 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 11.191m 321.779ms 50 50 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 11.121m 427.169ms 50 50 100.00
V2 stress_all spi_device_stress_all 20.908m 407.882ms 50 50 100.00
V2 alert_test spi_device_alert_test 0.780s 35.113us 50 50 100.00
V2 intr_test spi_device_intr_test 0.860s 29.729us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 5.310s 390.535us 20 20 100.00
V2 tl_d_illegal_access spi_device_tl_errors 5.310s 390.535us 20 20 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.510s 187.955us 5 5 100.00
spi_device_csr_rw 2.830s 189.828us 20 20 100.00
spi_device_csr_aliasing 24.570s 2.895ms 5 5 100.00
spi_device_same_csr_outstanding 4.720s 757.186us 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.510s 187.955us 5 5 100.00
spi_device_csr_rw 2.830s 189.828us 20 20 100.00
spi_device_csr_aliasing 24.570s 2.895ms 5 5 100.00
spi_device_same_csr_outstanding 4.720s 757.186us 20 20 100.00
V2 TOTAL 961 961 100.00
V2S tl_intg_err spi_device_sec_cm 1.120s 62.018us 5 5 100.00
spi_device_tl_intg_err 24.330s 4.165ms 20 20 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 24.330s 4.165ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 1101 1101 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 22 22 22 100.00
V2S 2 2 2 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.93 98.36 94.20 98.61 89.36 97.16 95.81 98.02

Past Results