SPI_DEVICE/2P Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: 349bab6601

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 12.038m 303.579ms 50 50 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.430s 171.313us 5 5 100.00
V1 csr_rw spi_device_csr_rw 2.670s 966.489us 20 20 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 39.150s 10.792ms 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 21.500s 621.650us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 3.790s 259.350us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.670s 966.489us 20 20 100.00
spi_device_csr_aliasing 21.500s 621.650us 5 5 100.00
V1 mem_walk spi_device_mem_walk 0.670s 17.945us 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 2.150s 775.298us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 csb_read spi_device_csb_read 0.850s 40.105us 50 50 100.00
V2 mem_parity spi_device_mem_parity 1.110s 51.974us 20 20 100.00
V2 mem_cfg spi_device_ram_cfg 0.760s 17.490us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 9.880s 204.725us 50 50 100.00
V2 tpm_write spi_device_tpm_rw 9.880s 204.725us 50 50 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 18.460s 22.095ms 50 50 100.00
spi_device_tpm_sts_read 1.020s 200.636us 50 50 100.00
V2 tpm_fully_random_case spi_device_tpm_all 1.026m 47.063ms 50 50 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 21.000s 7.125ms 50 50 100.00
spi_device_flash_all 10.179m 87.751ms 50 50 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 25.350s 8.877ms 50 50 100.00
spi_device_flash_all 10.179m 87.751ms 50 50 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 25.350s 8.877ms 50 50 100.00
spi_device_flash_all 10.179m 87.751ms 50 50 100.00
V2 cmd_info_slots spi_device_flash_all 10.179m 87.751ms 50 50 100.00
V2 cmd_read_status spi_device_intercept 24.960s 9.032ms 50 50 100.00
spi_device_flash_all 10.179m 87.751ms 50 50 100.00
V2 cmd_read_jedec spi_device_intercept 24.960s 9.032ms 50 50 100.00
spi_device_flash_all 10.179m 87.751ms 50 50 100.00
V2 cmd_read_sfdp spi_device_intercept 24.960s 9.032ms 50 50 100.00
spi_device_flash_all 10.179m 87.751ms 50 50 100.00
V2 cmd_fast_read spi_device_intercept 24.960s 9.032ms 50 50 100.00
spi_device_flash_all 10.179m 87.751ms 50 50 100.00
V2 cmd_read_pipeline spi_device_intercept 24.960s 9.032ms 50 50 100.00
spi_device_flash_all 10.179m 87.751ms 50 50 100.00
V2 flash_cmd_upload spi_device_upload 31.870s 10.721ms 50 50 100.00
V2 mailbox_command spi_device_mailbox 1.646m 13.163ms 50 50 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 1.646m 13.163ms 50 50 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 1.646m 13.163ms 50 50 100.00
V2 cmd_read_buffer spi_device_flash_mode 1.022m 5.110ms 50 50 100.00
spi_device_read_buffer_direct 26.510s 5.914ms 50 50 100.00
V2 cmd_dummy_cycle spi_device_mailbox 1.646m 13.163ms 50 50 100.00
spi_device_flash_all 10.179m 87.751ms 50 50 100.00
V2 quad_spi spi_device_flash_all 10.179m 87.751ms 50 50 100.00
V2 dual_spi spi_device_flash_all 10.179m 87.751ms 50 50 100.00
V2 4b_3b_feature spi_device_cfg_cmd 25.490s 9.235ms 50 50 100.00
V2 write_enable_disable spi_device_cfg_cmd 25.490s 9.235ms 50 50 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 12.038m 303.579ms 50 50 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 12.471m 420.012ms 50 50 100.00
V2 stress_all spi_device_stress_all 23.536m 311.352ms 50 50 100.00
V2 alert_test spi_device_alert_test 0.800s 15.073us 50 50 100.00
V2 intr_test spi_device_intr_test 0.800s 99.839us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 4.860s 1.170ms 20 20 100.00
V2 tl_d_illegal_access spi_device_tl_errors 4.860s 1.170ms 20 20 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.430s 171.313us 5 5 100.00
spi_device_csr_rw 2.670s 966.489us 20 20 100.00
spi_device_csr_aliasing 21.500s 621.650us 5 5 100.00
spi_device_same_csr_outstanding 4.480s 227.476us 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.430s 171.313us 5 5 100.00
spi_device_csr_rw 2.670s 966.489us 20 20 100.00
spi_device_csr_aliasing 21.500s 621.650us 5 5 100.00
spi_device_same_csr_outstanding 4.480s 227.476us 20 20 100.00
V2 TOTAL 961 961 100.00
V2S tl_intg_err spi_device_sec_cm 1.160s 144.877us 5 5 100.00
spi_device_tl_intg_err 21.130s 3.178ms 20 20 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 21.130s 3.178ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 1101 1101 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 22 22 22 100.00
V2S 2 2 2 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.95 98.35 94.20 98.61 89.36 97.14 95.81 98.17

Past Results